Dimitris P. Ioannou

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.

Positive Bias Temperature Instability Effects in nMOSFETs With

The positive bias temperature instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with SiO2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage (V T) instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, V T instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on V T instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.

\hbox{HfO}_{2}/\hbox{TiN}

The impact of SiO2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (VT) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.

Gate Stacks

Two methods of HfO2 nitridation including plasma N2 nitridation and thermal NH3 anneal were studied for ultrathin HfO2 gate dielectrics with <1 nm equivalent oxide thickness (EOT). The detailed nitridation mechanism, nitrogen depth profile, and nitrogen behavior during the anneal process were thoroughly investigated by XPS and SIMS analysis for the two types of nitridation processes at different process conditions. Intermediate metastable nitrogen was observed and found to be important during the plasma nitridation process. For thermal NH3 nitridation, pressure was found to be most critical to control the nitrogen profile while process time and temperature produced second order effects. The physical analyses on the impacts of various process conditions are well correlated to the electrical properties of the films, such as leakage current, EOT, mobility, and transistor bias temperature instability.

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FETs threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is frequency independent, an observation that suggests that VT degradation under AC stress can be equivalently measured through the simpler DC stress/relax sequence. An AC BTI model is developed that accurately captures the critical BTI relaxation effect through the DC stress/relax predictions on duty cycle dependence. A Ring Oscillator (RO) circuit is used as a model verification vehicle. Excellent agreement is demonstrated between the frequency degradation measurements obtained with a newly developed Ultra-Fast On-The-Fly (OTF) measurement technique optimized for BTI and the AC BTI model based RO simulations.

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness

Abstract We present a brief overview of Positive Bias Temperature Instability (PBTI) commonly observed in n-channel MOSFETs with SiO2/HfO2/TiN dual-layer gate stacks when stressed with positive gate voltage at elevated temperatures. We review the origin and present understanding of the characteristics of oxide traps that are responsible for the complex behavior of threshold voltage stability. We discuss the various physical mechanisms that are believed to govern the transient charging and discharging of these traps as the backbone of the models that have been proposed for PBTI degradation and recovery. Next we review the state-of-the-art in PBTI characterization and we present some of the key stress results on both the device as well the circuit level. Special emphasis is given on the open PBTI issues that need to be carefully addressed for a robust reliability methodology that accurately predicts PBTI lifetimes. Finally we mention some of the gate stack scaling effects on PBTI.

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS

With the introduction of High-k, metal gates and alternate substrates into the gate-stack at the 45nm and 32nm technology nodes, Bias Temperature Instability (BTI) phenomena have had to be included into the chip design modeling. In this paper, we explore BTI trends with High-k transistors in manufacturing ready CMOS processes with gate last and gate first type process flows. In both flows, Positive Bias Temperature Instability (PBTI) is a strong function of the interface and High-k thickness, with aggressive interface scaling having significant adverse reliability implications. Negative Bias Temperature Instability, on the other hand, is strongly dependent on the quality of the interface and its nitrogen content. The introduction of germanium into the Si channel is found to significantly improve NBTI. With recovery effects being strong in both NBTI and PBTI, AC BTI models in realistic circuit designs are critical to accurately evaluate the BTI lifetime of chips.

HKMG CMOS technology qualification: The PBTI reliability challenge

The impact of Bias Temperature Instability stress and poststress high temperature anneal (bake) effects on the performance of Ring Oscillator (RO) circuits is investigated for advanced node High-k Metal Gate (HKMG) and Oxynitride (SiON) based Silicon-On-Insulator (SOI) CMOS technologies. Examination of the circuit response (in terms of % frequency degradation) to a wide range of stress bias/temperature conditions reveals a distinct difference between the two technologies with respect to the voltage acceleration of frequency degradation. This difference is explained in view of the PBTI/NBTI voltage acceleration behaviour and indicates that PBTI dominates HKMG RO performance degradation. Post burn-in bake is found to be equally effective in recovering the burn-in induced frequency degradation in both HKMG and Oxynitride ROs. Finally, a simple model is proposed to predict net RO performance degradation from a combined burn-in/post-burn-in bake as a useful guideline for optimizing product burn-in testing.

Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends

We report that charge trapping has a strong impact on failure detection, yielding many anomalous non-Poisson area effects in nFETs high-κ stacks. Time-to-failure (TFAIL) distributions and voltage accelerations are found to strongly depend on stress waveforms such as interrupted DC stress and uninterrupted DC stress as well as unipolar and bipolar AC stress. Various correction methodologies such as SILC removal and voltage correction are considered to account for these adverse effects which are not present in SiO2 films.