Steven W. Mittl

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

This paper describes the combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFETs. Devices subjected to a 60-min, 400/spl deg/C, 10% deuterium/90% nitrogen anneal after silicidization show a 32/spl times/ improvement in hot-electron lifetime. These same devices are then passivated with a deuterated barrier-nitride layer formed using deuterated ammonia (ND/sub 3/) and conventional silane (SiH/sub 4/). Further deuterium anneals along with conventional contact and metal-level processes are used to integrate the devices. Hot-electron stressing and SIMS analysis performed at various points in the processing give insight to methods of retaining the beneficial effects of deuterium during subsequent thermal processing.

Accelerated gate-oxide breakdown in mixed-voltage I/O circuits

This paper describes a new mechanism of gate-oxide breakdown fails observed in mixed-voltage I/O circuits during an accelerated product stress. Although no gate-oxide breakdown was expected from Fowler-Nordheim stress, gate-oxide fails were observed only in short-channel PMOSFETs of the mixed-voltage I/O circuits. Accelerated gate-oxide breakdown was attributed to non-conductive channel hot-electron injection at the drain edge.

Positive Bias Temperature Instability Effects in nMOSFETs With

The positive bias temperature instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with SiO2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage (V T) instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, V T instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on V T instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.

\hbox{HfO}_{2}/\hbox{TiN}

The impact of SiO2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (VT) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.

Gate Stacks

Device level Self-Heating (SH) is becoming a limiting factor during traditional DC Hot Carrier stresses in bulk and SOI technologies. Consideration is given to device layout and design for Self-Heating minimization during HCI stress in SOI technologies, the effect of SH on activation energy (Ea) and the SH induced enhancement to degradation. Applying a methodology for SH temperature correction of extracted device lifetime, correlation is established between DC device level stress and AC device stress using a specially designed ring oscillator.

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FETs threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is frequency independent, an observation that suggests that VT degradation under AC stress can be equivalently measured through the simpler DC stress/relax sequence. An AC BTI model is developed that accurately captures the critical BTI relaxation effect through the DC stress/relax predictions on duty cycle dependence. A Ring Oscillator (RO) circuit is used as a model verification vehicle. Excellent agreement is demonstrated between the frequency degradation measurements obtained with a newly developed Ultra-Fast On-The-Fly (OTF) measurement technique optimized for BTI and the AC BTI model based RO simulations.

Self-heating and its implications on hot carrier reliability evaluations

The authors explore the impact of substrate hot carrier emission on the design of submicron FETs. Performance requirements increase the vertical field for decreasing feature size in the deep submicron regime. This in turn significantly enhances the degradation sensitivity to substrate hot carriers. Models that support reliability data show the relationship between device stability, and the location of the peak channel doping concentration with respect to the Si-SiO/sub 2/ interface. It is well established that increased surface concentration alone has the effect of increasing the rate of substrate hot carrier emission due to higher surface fields. These results show that an optimum design tradeoff of the apparently conflicting requirements of device stability, off-current and performance can be achieved by proper choice of doping peak location when key process tolerances are accounted for.<<ETX>>

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS

Both MOL PC-CA spacer dielectric and BEOL low-k dielectric breakdown data are commonly convoluted with multiple variables present in the data due to the involvement of many process steps such as lithography, etch, CMP, cleaning, and thin film deposition. With the continuing aggressive scaling of device dimensions and introduction of new device configurations, how to accurately analyze such complicated lateral dielectric breakdown data from MOL and BEOL TDDB in advanced VLSI circuits has become very challenging. In this paper, a new electrical method is developed to accurately characterize different variables in MOL and BEOL dielectric breakdown. This method provides a powerful way to do a fast deep dive process and reliability analysis for technology development and qualification without time consuming physical failure analysis.

Doping profile design for substrate hot carrier reliability in deep submicron field effect transistors

Contrary to recent claims, experimental results obtained in thin and thick Hafnium-based high-K gate dielectric stacks demonstrate that progressive breakdown is relevant in these insulators. For thin and thick stacks and both in NFETs and PFETs, the residual time distributions are found to be non-Weibull with two regions: a universally shallower slope at long times and a steeper slope at short times. The shallow distributions favour the coexistence of single-spot BD and multiple competing spots in different samples. Contrary to what happens in the case of SiON dielectrics, the final failure distribution is reported to be strongly dependent on the threshold current IF used to define device failure. Also contrary to what found for SiON single-layer dielectrics, the voltage acceleration and temperature activation energy of the residual time is reported to be much stronger than that of the first breakdown time. All these results emphasize the important role of progressive breakdown for high-K reliability assessment methodology.

New electrical testing structures and analysis method for MOL and BEOL process diagnostics and TDDB reliability assessment

High-performance CMOS products depend upon the reliability of ultrathin gate dielectrics. In this paper a methodology for measuring thin gate dielectric reliability is discussed in which the focus is upon the elements of those test structures used in the evaluation, the design of the reliability stress matrix, and the generation of engineering design models. Experimental results are presented which demonstrate the reliability of ultrathin gate dielectrics measured on a wide variety of test structures with dielectric thicknesses ranging from 7 to 3.5 nm. An overview is provided for thin gate oxide reliability that was measured on integrated functional chips-high-performance microprocessors and static random-access memory (SRAM) chips. The data from these measurements spanned the period from early process and device development to full production. Manufacturing in-line monitoring for thin gate dielectric yield and reliability is also discussed, with several case histories presented which show the effectiveness of monitors in detecting process-induced dielectric failures. Finally, causes of oxide fails are discussed, leading to the process actions necessary for controlling thin gate dielectric defects.