Ernest Y. Wu

Ultra-thin oxide reliability for ULSI applications

In this article, we critically examine the limit of gate oxide scaling from a reliability point of view. The thickness dependence of the characteristic breakdown time (charge) and Weibull slope as well as the temperature dependence of oxide breakdown are measured with emphasis on accuracy. The failure modes of soft and hard breakdown events and their impact on device characteristics are reviewed. Using a two-dimensional reliability analysis, we explore the relative importance of characteristic breakdown time and Weibull slope in lifetime projection, and the possibilities of extending gate oxide beyond the currently predicted limit.

On the Weibull shape factor of intrinsic breakdown of dielectric films and its accurate experimental determination. Part I: theory, methodology, experimental techniques

Critically examined several important aspects concerning the experimental determination of Weibull shape factors (slopes). Statistical characteristics of breakdown distribution such as area scaling property and the extreme-value distribution are reviewed. We discuss the experimental measurement methodology of time-to-breakdown (T/sub BD/) or charge-to-charge (Q/sub BD/) distributions with the emphasis on the accuracy. The influence of sample numbers on the estimation of Weibull distribution parameters such as characteristic T/sub BD/ and Weibull slopes are investigated in the context of confidence limits. Some examples of the measurement fallacy on Weibull slopes are given. Three different experimental techniques to measure Weibull slopes are described and compared in terms of their advantages and disadvantages. Finally, we will give a comparison of these three methods. Having established these fundamental aspects of the Weibull slope measurements, we will present our extensive experimental data on thickness, voltage, temperature, and polarity dependence of Weibull slopes in part II.

Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides

In this paper, we present experimental evidence on the voltage-dependence of the voltage acceleration factors observed on ultrathin oxides from 5 nm down to /spl sim/1 nm over a wide range of voltages from /spl sim/2 V to 6 V. Two independent experimental approaches, area scaling method and long-term stress, are used to investigate this phenomenon. We show the exponential law with a constant voltage-acceleration factor violates the widely accepted fundamental breakdown property of Poisson random statistics while the voltage-dependent voltage acceleration described by an empirical power-law relation preserves this well-known property. The apparent thickness-dependence of voltage acceleration factors measured in different voltage ranges can be nicely understood and unified with these independent experimental results in the scenario of a voltage-driven breakdown. In the framework of the critical defect density and defect generation rate for charge-to-breakdown, we explore the possible explanation of increasing voltage acceleration factors at reduced voltage by assuming a geometric model for the critical defect density.

Voltage-dependent voltage-acceleration of oxide breakdown for ultra-thin oxides

We report the voltage-dependence of voltage acceleration for ultra-thin oxides from 2.2 V to 5 V over a range of T/sub ox/ values from 1.7 nm to 5.0 nm. This unique behavior manifest itself as a power-law voltage-dependence for time-to-breakdown (T/sub BD/) over a variety of experimental observations. Using the concept of energy-to-breakdown, we explore the possible scenarios such as fractional energy or defect generation probability as a function of voltage to account for the increase in voltage acceleration with decreasing voltages.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure

For the first time, we report strong channel-length dependence and weak channel-width dependence of soft breakdown modes and device failure for ultra-thin gate oxides. For channel lengths around 0.2 /spl mu/m, oxide-breakdown events in FETs cause a sharp increase in FETs off-current which permanently degrades the switching performance of short-channel devices; this is not observed for longer channel length FETs. The results also indicate that both hard- and soft-breakdown events have a common origin but manifest themselves differently depending on the test structure and geometry being measured.

Gate oxide breakdown under Current Limited Constant Voltage Stress

Ultra-thin oxide reliability has become an important issue in integrated circuit scaling. Present reliability methodology stresses oxides with a low impedance voltage source. This, though, does not represent the stress under circuit configurations, in which transistors are driven by other transistors. A Current Limited Constant Voltage Stress simulates circuit stress well. Limiting the current during the breakdown event reduces the post-breakdown conduction. Limiting the current to a sufficiently low value may prevent device failure, altogether.

Challenges for accurate reliability projections in the ultra-thin oxide regime

In this work, we discuss several important aspects of reliability projections, especially for ultra-thin oxides in a direct tunneling regime such as stress methodologies, the determination of projection parameters, and their dependence on stress conditions as well as their impact on reliability projection. Most importantly, we found that the Weibull shape factors and area dependence are key to understanding of the reliability limitations for ultra-thin oxides.

Statistics of successive breakdown events in gate oxides

The basic statistics for devices/circuits that can tolerate several breakdown (BD) events without failure are derived. All the presented results are analytical and do not rely on the validity of any model relating breakdown to defect generation. The single requirement is the uniform and uncorrelated generation of breakdown paths. Significant lifetime improvement is anticipated for low failure percentiles and Weibull slopes close to unity, as those found in oxides with the thickness required for sub-100-nm CMOS technologies. The presented results are validated using grouping experiments.

CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics

The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulators.