anming Li

Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank

A 60 GHz voltage-controlled oscillator with an inductive division LC tank has been designed in 90 nm CMOS. The analysis of the oscillator shows that the presence of higher harmonics, the capacitance nonlinearity and the very high K VCO are critical for the phase noise performance of oscillators. Therefore, a pseudo-differential amplifier is employed in this design because of its high linearity. Furthermore, the proposed inductive division reduces the phase noise by increasing the signal amplitude across the varactor, without affecting the operation mode of the cross-coupled pair transistors. It also helps to increase the tuning range by isolating the varactor from the parasitic capacitances of the transistors and interconnects. The mm-wave oscillator is fabricated in a 90 nm CMOS technology. Under 0.7 V supply, the oscillator achieves a tuning range from 53.2 GHz to 58.4 GHz, consuming 8.1 mW. At 58.4 GHz, the phase noise is -91 dBc/Hz at 1 MHz offset. Under 0.43 V supply, the oscillator achieves a tuning range from 58.8 to 61.7 GHz. At 61.7 GHz, the phase noise is -90 dBc/Hz @1& MHz offset with a power consumption of only 1.2 mW.

A 60-GHz CMOS VCO Using Capacitance-Splitting and Gate–Drain Impedance-Balancing Techniques

The design and measurement of a 60-GHz 90-nm CMOS voltage-controlled oscillator is presented. To reduce the power consumption and to improve the phase-noise performance, a capacitance-splitting and a gate-drain impedance-balancing techniques, which are realized with an inductive divider, are proposed. With these techniques, the size of the cross-coupled pair is reduced. Analysis of the proposed techniques shows that the transistor g m generation efficiency is improved and the oscillator noise factor is reduced. Moreover, the tank loaded quality factor is increased by balancing impedance levels across the transistor terminals. The 60-GHz oscillator was fabricated in a 90-nm CMOS technology. Under 0.6-V supply, the oscillator achieved a tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At 64 GHz, the phase noise is -95 dBc/Hz at 1-MHz offset.

A low power mm-wave oscillator using power matching techniques

A low power low voltage 90nm CMOS mm-wave oscillator using a power matching technique is presented. The oscillator uses an inductive divider to create impedance matching for the amplifier. With this technique, the effect of the varactor loss on the phase noise is reduced and the oscillator power efficiency is increased. The proposed oscillator achieves a phase noise of −95dBc/Hz at 1MHz offset from 64GHz carrier, consuming 3.16 mW from a 0.6 V supply voltage. The figures-of-merit are FOM −186 and FOMT −185 respectively. The tuning range is from 61.1 GHz to 66.7 GHz and the measured output power is about −14 dBm.

A 60GHz 15.7mW static frequency divider in 90nm CMOS

Two millimeter-wave current mode logic (CML) flip-flop-based static frequency dividers, divide-by-4 and by-2, are realized in a 90nm bulk CMOS. In order to achieve a large locking range and a high operating speed, capacitive-bridged shunt peaking techniques are implemented by taking advantage of the parasitic capacitance. The first flip-flop in these two dividers can directly drive the second flip-flop to save power, resulting in a power consumption as low as of 15.7mW from a 1.2V supply. Their input referred self-resonance frequencies are 57.6GHz and 61.4GHz respectively. Taking into account that all this is achieved in bulk CMOS, and even compared to SOI designs, the achieved power consumption is the lowest reported.

A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques

A 60 GHz Colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques is realized in 90 nm CMOS. With the Miller capacitance, the tuned-input tuned-output oscillator and the conventional Colpitts oscillator are combined together, thereby solving its start-up issues and improving phase noise performance. Moreover, it is found that the oscillator is robust to the tank mistuning. The proposed oscillator achieves a phase noise of −102 dBc/Hz at 1 MHz offset from 57.6 GHz, consuming 7.2 mW from a power supply of 0.6 V. The tuning range is from 55.8 GHz to 61.1 GHz and the measured single-ended output power is about −7 dBm. Accordingly, the figures-of-merit are FOM −189 and FOMT −188 respectively.

60GHz power amplifier with distributed active transformer and local feedback

A 52–61 GHz power amplifier (PA) is implemented in 65nm CMOS bulk technology. The distributed active transformer (DAT) combines the output power from two unit PAs and achieves a peak output power of 14.8 dBm. Each unit PA uses two-stage differential cascode topology. This PA achieves a peak power gain of 10.2 dB with 10.8 dBm 1-dB compression output power (OP1dB) and a peak power-added efficiency (PAE) of 7.2%. The transformer based passives enable a compact active area of 0.3mm2. This PA consumes a quiescent current of 143mA from a 1.6V supply voltage. Thanks to the linearization of last stage, the OP1dB can be further improved to 11.8 dBm when the drivers supply voltage increases to 2.2V.

A 90nm CMOS mm-wave VCO using an LC tank with inductive division

This paper presents a low supply voltage, fundamental-frequency 90 nm CMOS mm-wave oscillator using an enhanced LC tank with inductive division to improve the oscillator performance. The oscillator achieves a tuning range from 53.2 GHz to 58.4 GHz while consuming 8.1 mW from a 0.7 V supply. The phase noise at 58.4 GHz is -90.08 dBc/Hz @ 1 MHz offset. The oscillator can also be operated from a supply voltage as low as 0.43 V with a phase noise of -90.10 dBc/Hz @ 1 MHz offset from a 61.7 GHz carrier, while consuming only 1.2 mW.