Do-Bin Kim

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

In this letter, we propose a simplified channel stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to targeted the Vth values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the Vth values of SSTs are set to the targeted Vth values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the Vth values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).

Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (Vth) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted Vth values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the Vth values of SSTs/DSSTs are set to the targeted Vth values by the new methods and SSTs with extremely narrow Vth distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the Vth values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.

Investigation of self boosting disturbance induced by channel coupling in 3D stacked NAND flash memory

As the needs for high density NAND flash memory have been dramatically increasing, the memory density has also increased by scaling down the technology node. As the scaling of NAND flash memory is accelerated, the short channel effect is more severe and further scaling down is faced with process limitations. So, various types of 3D stacked NAND flash memory has been introduced and reported for ultra-high-density data storage and Fig. 1 shows one of the previously reported 3D stacked NAND flash memory structures [1–3]. However, as the distance between layers is reduced, several channel coupling problems are emerging. In this paper, we investigate the self boosting disturbance induced by channel coupling between layers in the 3D stacked NAND flash memory.

Interface and oxide trap analysis at tunnel oxide of NAND flash memory with excluding the effect of floating gate

Charge trap characteristic at tunneling oxide of floating gate NAND flash observed after program/erase (P/E) cycling. At initial P/E cycling, acceptor-like interface traps and positive oxide traps are generated simultaneously but the effect of interface trap is dominant and consequently threshold voltage increase. However, once the interface traps are generated, change of interface trap is negligible under program or erase operation and threshold voltage variation mainly depends on oxide traps. Additionally, voltage acceleration factor of threshold voltage change at low erase voltage is extracted for relative reliability test of NAND flash memory devices.

Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed structure can maximize memory density, since additional SSTs are not required for layer selection and the placement of BLs/word lines is similar to that of the conventional NAND array except for island-type GSTs. Basic memory operations are performed with fabricated devices. The selected layer is erased only by applying erase voltage to the selected common source line (CSL) and by biasing inhibition voltage to other CSLs. Only the selected layer is read by applying the same voltage as BL voltage to the CSLs of the unselected layers. In addition, the selected strings in the selected layer are programmed and other strings in the selected and unselected layers are all inhibited by the combination of CSL and BL voltages. Consequently, stable memory operations are obtained successfully in the proposed structure without interference between stacked layers.

A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.