Wandong Kim

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (Vth) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO2 at the edge regions along the channel length/width directions and that a negative Vth shift is derived from hole trapping in the gate insulator far from the SiO2/HIZO interface.

Temperature effect on negative bias-induced instability of HfInZnO amorphous oxide thin film transistor

Negative bias-induced instability of amorphous hafnium indium zinc oxide (α-HIZO) thin film transistors (TFTs) was investigated at various temperatures. In order to examine temperature-induced effects, fabricated TFTs with different combinations of gate insulator and gate metal were stressed by a negative gate bias at various temperatures. As a result, it is proved that negative bias-induced hole-trapping in the gate insulators and temperature-enhanced electron injection from the gate metals occurs at the same time at all temperatures, and the instability of HIZO TFT is more affected by the dominant factor out of the two mechanisms.

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer selection performed by the bias of SSL, the placement of bit lines and word lines is similar to the conventional planar structure, and proposed CSTAR with LSM has no island-type SSLs. As a result of the advantages of the proposed architecture, various issues of conventional channel stacked NAND flash memory array can be solved.

A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure

In order to overcome the limitation of a multibit silicon-oxide-nitride-oxide-silicon (SONOS) memory with multistorage nodes, we propose a unique 3-D vertical NOR (U3VNOR) array architecture. The U3VNOR has a vertical channel so that it is possible to have a long enough channel without extra cell area. Therefore, we can avoid the problems such as redistribution of injected charges, second-bit effect, and short-channel effect. Also, it is the most integrated flash architecture having the smallest unit cell size, which is 1 F2/bit. In this paper, we present the fabrication method and the operation voltage scheme of the U3VNOR. In addition, through numerical simulation, we verify its program and erase characteristics. Due to its high density and reliable multibit operation, the U3VNOR is a promising structure for the future high-density NOR flash memory.

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

In this letter, we propose a simplified channel stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to targeted the Vth values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the Vth values of SSTs are set to the targeted Vth values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the Vth values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

In this letter, a novel SONOS NAND Flash memory array featuring arch-shaped silicon fin and extended word lines (WL) is proposed to improve virtual source/drain (VSD) performance. The arch shape concentrates electric field, resulting in higher electron concentration at the VSD region and higher on -state cell current. In addition, the extended WL process improves the short-channel-effect (SCE) immunity and I-V characteristics. To verify these, an arch VSD NAND array device was fabricated and characterized. The integrated device shows very small SCE while obtaining high on-state cell current. Program and disturbance characteristics of the device are also confirmed.

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon–oxide–nitride–oxide–silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler–Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30×70 nm2 (L×W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7 nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).