Joo Yun Seo

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the VT variation among cells and reduce the total programming time.

Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

In this letter, we propose a layer selection method by permutations (LSMPs) of string select line (SSL) bias and string select transistor with multi-level states. Due to the increased number of threshold voltage orderings by the permutation, the number of required SSLs for the layer selection and the space occupied by SSLs can be minimized. Also, the operation scheme for the layer selection is discussed. To verify the operation of proposed LSMP, a fabricated pseudo-LSM is measured. As a result, it is clearly revealed that the number of selectable layer can be increased drastically by the LSMP.

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer selection performed by the bias of SSL, the placement of bit lines and word lines is similar to the conventional planar structure, and proposed CSTAR with LSM has no island-type SSLs. As a result of the advantages of the proposed architecture, various issues of conventional channel stacked NAND flash memory array can be solved.

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

In this letter, we propose a simplified channel stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to targeted the Vth values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the Vth values of SSTs are set to the targeted Vth values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the Vth values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

New program inhibition scheme for high boosting efficiency in three-dimensional NAND array

In this work, program inhibition in a three-dimensional (3D) NAND array has been studied by technology computer-aided design (TCAD) simulation. Results indicate a variation in boosting efficiency among unselected channels with respect to their bias conditions. This variation can cause severe program disturbance in a NAND array. To reduce this potential variation, a new method that guarantees a reliable program inhibition has been designed. With this new scheme, the unwanted threshold voltage (VTH) shift of unselected cells induced by program disturbance can be notably reduced.

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).

A tunneling field-effect transistor using side metal gate/high-k material for low power application

Supply voltage (VDD) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1–2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported [3]. Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO2 in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.

Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (Vth) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted Vth values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the Vth values of SSTs/DSSTs are set to the targeted Vth values by the new methods and SSTs with extremely narrow Vth distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the Vth values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.