Donald J. Sauer

Uncooled IR imager with 5-mK NEDT

The bi-material concept for room-temperature infrared imaging has the potential of reaching an NE(Delta) T approaching the theoretical limit because of its high responsivity and low noise. The approach, which is 100% compatible with silicon IC foundry processing, utilizes a novel combination of surface micromachining and conventional integrated circuits to produce a bimaterial thermally sensitive element that controls the position of a capacitive plate coupled to the input of a low noise MOS amplifier. This approach can achieve the high sensitivity, the low weight, and the low cost necessary for equipment such as helmet mounted IR viewers and IR rifle sights. The pixel design has the following benefits: (1) an order of magnitude improvement in NE(Delta) T due to extremely high sensitivity and low noise, (2) low cost due to 100% silicon IC compatibility, (3) high image quality and increased yield due to ability to do offset and sensitivity corrections on the imager, pixel-by-pixel; (4) no cryogenic cooler and no high vacuum processing; and (5) commercial applications such as law enforcement, home security, and transportation safety. Two designs are presented. One is a 50 micrometer pixel using silicon nitride as the thermal isolation element that can achieve 5 mK NE(Delta) T; the other is a 29 micrometer pixel using silicon carbide that provides much higher thermal isolation and can achieve 10 mK NE(Delta) T.

Progress toward an uncooled IR imager with 5-mK NETD

The bi-material concept for room-temperature infrared imaging has the potential of reaching an NE(Delta) T approaching the theoretical limit because of its high responsivity and low noise. The approach, which is 100% compatible with silicon IC foundry processing, utilizes a novel combination of surface micromachining and conventional integrated circuits to produce a bimaterial thermally sensitive element that controls the position of a capacitive plate coupled to the input of a low noise MOS amplifier. This approach can achieve the high sensitivity, the low weight, and the low cost necessary for equipment such as helmet-mounted IR viewers and IR rifle sights. The pixel design has the following benefits: (1) an order of magnitude improvement in NE(Delta) T due to extremely high sensitivity and low noise; (2) low cost due to 100% silicon IC compatibility; (3) high image quality and increased yield due to ability to do offset and sensitivity corrections on the imager, pixel-by-pixel; (4) no cryogenic cooler and no high vacuum processing; (5) commercial applications such as law enforcement, home security, and transportation safety.

640 x 480 element PtSi IR sensor with low-noise MOS X-Y addressable multiplexer

The design of a 640 by 480 element PtSi IR sensor is presented which includes a low-noise MOS X-Y addressable readout multiplexer and an on-chip correlated double-sampling amplifier. The sensor is designed to load scan data into CMOS horizontal and vertical scanning registers by means of a multiplexed horizontal/vertical input address port and onchip decoding, allowing any element in the focal plane array to be randomly accessed. The FPA is shown to be operable in both the interlaced and noninterlaced formats, with variable exposure control. Enhanced noise performance is shown due to the use of buried channel source follower buffers in the horizontal signal lines. It was shown that 24 micron square pixels with a 1.5 micron double level metal CMOS process provide a fill factor of 38 percent. TTL compatibility and ESD protection diodes are key features of the digital inputs to the sensors chip.

High fill-factor CCD imager with high frame-rate readout

The design for two high fill-factor CCD arrays for optical signal processing applications is described. The imaging registers have 1024 x 1024 and 512 x 512 pixels and achieve virtually 100 percent optical fill factor through the use of substrate thinning and back illumination. High frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports resulting in reduced readout frequency. On-chip correlated double sampling amplifiers are implemented to reduce the readout noise and simplify off-chip analog signal processing. Both chips include antiblooming drain structures and ESD protection circuits.

Performance of high-frame-rate, back-illuminated CCD imagers

A second generation of high-frame-rate 512 X 512 and 1024 X 1024 pixel CCD imagers has been fabricated. These thinned, back-illuminated frame transfer imagers, designed for optical signal-processing applications, employ a split-frame transfer into dual storage registers and multiple output ports for increased frame rates. Reported here are measured characteristics of 16-port 512 X 512 and 32-port 1024 X 1024 imagers from the second design/fabrication cycle. Data are presented characterizing quantum efficiency, dynamic range, antiblooming control operation, high-speed performance, and on-chip correlated-double-sampling amplifier noise.

Performance of generation III 640 x 480 PtSi MOS array

The design and performance of a third generation 640(H) X 480(V) PtSi focal plane array is presented. The 3 to 5 micron MWIR focal plane array supports interlaced, progressive scan, and subframe readout under control of on-chip digital decoders. The new design utilizes 1.25 micrometers design rules to achieve a 50% fill-factor, a noise equivalent delta temperature of <0.07 C (f/1.5, 30 Hz, 300 K), and a saturation level >1.5 X 106e. The power dissipation is less than 110 mW.

Performance of a high-frame-rate CCD imager

Back-illuminated, 16-port 512 X 512 and 32-port 1024 X 1024 charge coupled device (CCD) imagers have been fabricated. The measured performance of the 512 X 512 pixel chip is described, including data on quantum efficiency, dynamic range, dark current, frame rates, uniformity, contrast transfer function, and on-chip correlated double- sampling (CDS) amplifier noise. We have previously reported on these designs. The CCD arrays are designed with a unique combination of parameters optimized for applications requiring high resolution combined with high frame rates and wide dynamic range. The imaging registers achieve 100% optical fill factor and high quantum efficiency through the use of substrate thinning and back-side illumination. The high frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports which reduce the 512 X 512 array readout frequency to 15 MHz for 800 frame per second operation. On- chip CDS amplifiers are included in each output port to reduce the readout noise and simplify off-chip analog signal processing. Both designs include a buried anti-blooming drain structure and electro static discharge (ESD) protection.

Multiport backside-illuminated CCD imagers for high-frame-rate camera applications

Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.

Radiation-hardened backside-illuminated 512 x 512 charge-coupled device

A four-port 512 X 512 charge coupled device (CCD) imager hardened against proton displacement damage and total dose degradation has been fabricated and tested. The device is based upon an established thinned, backside illuminated, triple polysilicon, buried channel CCD process technology. The technology includes buried blooming drains. A three step approach has been taken to hardening the device. The first phase addressed hardening against proton displacement damage. The second phase addressed hardening against both proton displacement damage and total dose degradation. The third phase addresses final optimization of the design. Test results from the first and second phase efforts are presented. Plans for the third phase are discussed.

640 x 480 MWIR and LWIR camera system developments

The performance of a 640 x 480 PtSi, 3,5 microns (MWIR), Stirling cooled camera system with a minimum resolvable temperature of 0.03 is considered. A preliminary specification of a full-TV resolution PtSi radiometer was developed using the measured performance characteristics of the Stirling cooled camera. The radiometer is capable of imaging rapid thermal transients from 25 to 250 C with better than 1 percent temperature resolution. This performance is achieved using the electronic exposure control capability of the MOS focal plane array (FPA). A liquid nitrogen cooled camera with an eight-position filter wheel has been developed using the 640 x 480 PtSi FPA. Low thermal mass packaging for the FPA was developed for Joule-Thomson applications.