Frank V. Shallcross

160 × 244 Element PtSi Schottky-barrier IR-CCD image sensor

A 160 × 244 element IR-CCD image sensor was developed with PtSi Schottky-barrier detectors (SBDs) for thermal imaging in the 3.0-5.0-µm IR band. This imager has 80 × 40 µm2pixels, a fill factor of 39 percent, and a chip size of 584 × 464 mil2. It produces excellent quality thermal imaging with noise-equivalent temperature (NEΔT) of less than 0.1 K for operation at 30 frames/s with standard-TV-interlace f/2.3 optics, and one-point offset-type uniformity corrector. This paper describes the design, construction, and performance of 160 × 244 element IR-CCD imager and the characteristics of the PtSi Schottky-barrier detector elements.

360/spl times/360-element very-high-frame-rate burst image sensor

A 360/spl times/360-element very high frame rate (VHFR) burst image sensor captures images at maximum frame rate up to 10/sup g/ frame/s. This is accomplished by continuously storing the last 30 image frames at the pixel locations. The 360/spl times/360 VHFR imager having a 2/spl times/2 cm/sup 2/ chip is designed in the form of 4 quadrants each with 180/spl times/180 pixels. Each pixel occupies 50/spl times/50 /spl mu/m/sup 2/ and consists of a 337 /spl mu/m/sup 2/ photodetector with a fill factor of 13.5% and a S-phase 30-stage (5/spl times/6) series-parallel type buried-channel CCD (BCCD) register for continuously storing the last 30 detected image frames. The chip uses 1.5 /spl mu/m design rules and 1.5/spl times/3 /spl mu/m/sup 2/ minimum-size BCCD storage elements.

360/spl times/360 element three-phase very high frame rate burst image sensor: design, operation and performance

Design, fabrication, operation and performance are described for a 360/spl times/360 element very high frame rate (VHFR) image sensor that can capture images at a frame rate of up to 10/sup 6/ frames/s. This VHFR imager has 50/spl times/50 /spl mu/m macropixels, each consisting of a high-speed zero-lag photodetector with a 13.5% fill factor and 30 stages of serial-parallel type buried-channel CCD registers for storage and readout of the last 30 image frames acquired. Readout of this imager is similar to a frame transfer CCD consisting of four quadrants. Each quadrant contains one million pixels, readout at a relatively slow rate compatible with low readout noise, and PC class microcomputer-based data acquisition and storage. This imager is designed using SiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric, four levels of polysilicon, three levels of metal, eight implants, 21 photo masks using 1.5-/spl mu/m design rules, and it has four output ports. The high-speed photodetector is designed in the form of a graded three-potential-level pinned-buried BCCD structure. This 33-/spl mu/m long photodetector can achieve complete readout of photogenerated electrons in less than 0.1 /spl mu/s.

640 x 480 element PtSi IR sensor with low-noise MOS X-Y addressable multiplexer

The design of a 640 by 480 element PtSi IR sensor is presented which includes a low-noise MOS X-Y addressable readout multiplexer and an on-chip correlated double-sampling amplifier. The sensor is designed to load scan data into CMOS horizontal and vertical scanning registers by means of a multiplexed horizontal/vertical input address port and onchip decoding, allowing any element in the focal plane array to be randomly accessed. The FPA is shown to be operable in both the interlaced and noninterlaced formats, with variable exposure control. Enhanced noise performance is shown due to the use of buried channel source follower buffers in the horizontal signal lines. It was shown that 24 micron square pixels with a 1.5 micron double level metal CMOS process provide a fill factor of 38 percent. TTL compatibility and ESD protection diodes are key features of the digital inputs to the sensors chip.

High fill-factor CCD imager with high frame-rate readout

The design for two high fill-factor CCD arrays for optical signal processing applications is described. The imaging registers have 1024 x 1024 and 512 x 512 pixels and achieve virtually 100 percent optical fill factor through the use of substrate thinning and back illumination. High frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports resulting in reduced readout frequency. On-chip correlated double sampling amplifiers are implemented to reduce the readout noise and simplify off-chip analog signal processing. Both chips include antiblooming drain structures and ESD protection circuits.

Schottky-barrier image sensor with 100% fill factor

A new concept, the Direct Schottky Injection (DSI), is described for a three-dimensional construction of infrared imagers with a continuous Schottky-barrier-detector surface on one side of a thinned (10 to 25 microns) silicon substrate and p-type buried-channel CCD readout structure on the other side. The DSI structure provides a 100-percent fill factor, a large charge-handling capacity, and a high-density pixel design. The construction and operation are described for DSI imagers with frame-transfer CCD (FT-CCD) and interline-transfer CCD(IT-CCD) readout. The operation of the IT-CCD DSI imager was demonstrated with a 128 x 128 focal plane array (FPA) with 50 x 50-micron pixels.

Performance of high-frame-rate, back-illuminated CCD imagers

A second generation of high-frame-rate 512 X 512 and 1024 X 1024 pixel CCD imagers has been fabricated. These thinned, back-illuminated frame transfer imagers, designed for optical signal-processing applications, employ a split-frame transfer into dual storage registers and multiple output ports for increased frame rates. Reported here are measured characteristics of 16-port 512 X 512 and 32-port 1024 X 1024 imagers from the second design/fabrication cycle. Data are presented characterizing quantum efficiency, dynamic range, antiblooming control operation, high-speed performance, and on-chip correlated-double-sampling amplifier noise.

Performance of generation III 640 x 480 PtSi MOS array

The design and performance of a third generation 640(H) X 480(V) PtSi focal plane array is presented. The 3 to 5 micron MWIR focal plane array supports interlaced, progressive scan, and subframe readout under control of on-chip digital decoders. The new design utilizes 1.25 micrometers design rules to achieve a 50% fill-factor, a noise equivalent delta temperature of <0.07 C (f/1.5, 30 Hz, 300 K), and a saturation level >1.5 X 106e. The power dissipation is less than 110 mW.

A photoconductive sensor for card readers

An experimental thin-film CdS:CdSe photoconductordiode array having 80 × 12 elements has been fabricated by vacuum deposition on a single 4 × 8 inch substrate. Element spacing is the same as the hole positions in a standard computer punched card. Possible applications include static and dynamic card readers.

Multiport backside-illuminated CCD imagers for high-frame-rate camera applications

Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.