Grazyna M. Meray

Large format backside illuminated CCD imager for space surveillance

The key features and performance data of a 2560/spl times/1960-pixel split-frame-transfer imager developed for space surveillance is described. The eight-port, backside illuminated charge coupled device (CCD) features 24 /spl mu/m pixels with buried blooming drains to provide 100% optical fill-factor and >1000/spl times/ overload protection from blooming. The imaging and storage registers are strapped with metal to achieve vertical transfer clock rates >400 KHz for the 61 mm long imaging register gates. The 5 million pixel array operates at 2.7 frames/s. The monolithic focal plane includes a 32/spl times/32-pixel frame-transfer imager, with a single output, which operates at 1000 frames/s. The output ports employ a floating diffusion output circuit with responsivity of 10.5 /spl mu/V/e and noise of 7e RMS at a 1.25 MHz clock rate. The imager is photocomposed employing a combination of 5/spl times/ and 1/spl times/ lithography. The photocomposition approach is described.

Construction And Performance Of A 320 X 244-Element IR-CCD Imager With PtSi Schottky-Barrier Detectors

A 320 x 244-element IR-CCD imager was developed with 40μm x 40-μm pixels, 43% fill factor, and a saturation signal of 1.4 x 106 electrons/pixel. Charge-transfer inefficiency of less than 10-4 per transfer was achieved for operation of the imager at 77K with horizontal clock frequency of 6.2 MHz using a 12-μm-wide horizontal output register with a 3-μm-wide trench. The device was operated at temperatures as low as 50K with sufficiently low transfer losses to produce good quality video images. Excellent quality thermal imaging was demonstrated for operation of the 320 x 244 imager at 30 frames/s with 100 mm f/1.4 lens, an f/1.3 cold shield, and 3.4-μm long-pass filter at 77K.

640 x 480 element PtSi IR sensor with low-noise MOS X-Y addressable multiplexer

The design of a 640 by 480 element PtSi IR sensor is presented which includes a low-noise MOS X-Y addressable readout multiplexer and an on-chip correlated double-sampling amplifier. The sensor is designed to load scan data into CMOS horizontal and vertical scanning registers by means of a multiplexed horizontal/vertical input address port and onchip decoding, allowing any element in the focal plane array to be randomly accessed. The FPA is shown to be operable in both the interlaced and noninterlaced formats, with variable exposure control. Enhanced noise performance is shown due to the use of buried channel source follower buffers in the horizontal signal lines. It was shown that 24 micron square pixels with a 1.5 micron double level metal CMOS process provide a fill factor of 38 percent. TTL compatibility and ESD protection diodes are key features of the digital inputs to the sensors chip.

High fill-factor CCD imager with high frame-rate readout

The design for two high fill-factor CCD arrays for optical signal processing applications is described. The imaging registers have 1024 x 1024 and 512 x 512 pixels and achieve virtually 100 percent optical fill factor through the use of substrate thinning and back illumination. High frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports resulting in reduced readout frequency. On-chip correlated double sampling amplifiers are implemented to reduce the readout noise and simplify off-chip analog signal processing. Both chips include antiblooming drain structures and ESD protection circuits.

Schottky-barrier image sensor with 100% fill factor

A new concept, the Direct Schottky Injection (DSI), is described for a three-dimensional construction of infrared imagers with a continuous Schottky-barrier-detector surface on one side of a thinned (10 to 25 microns) silicon substrate and p-type buried-channel CCD readout structure on the other side. The DSI structure provides a 100-percent fill factor, a large charge-handling capacity, and a high-density pixel design. The construction and operation are described for DSI imagers with frame-transfer CCD (FT-CCD) and interline-transfer CCD(IT-CCD) readout. The operation of the IT-CCD DSI imager was demonstrated with a 128 x 128 focal plane array (FPA) with 50 x 50-micron pixels.

Performance of high-frame-rate, back-illuminated CCD imagers

A second generation of high-frame-rate 512 X 512 and 1024 X 1024 pixel CCD imagers has been fabricated. These thinned, back-illuminated frame transfer imagers, designed for optical signal-processing applications, employ a split-frame transfer into dual storage registers and multiple output ports for increased frame rates. Reported here are measured characteristics of 16-port 512 X 512 and 32-port 1024 X 1024 imagers from the second design/fabrication cycle. Data are presented characterizing quantum efficiency, dynamic range, antiblooming control operation, high-speed performance, and on-chip correlated-double-sampling amplifier noise.

Performance of generation III 640 x 480 PtSi MOS array

The design and performance of a third generation 640(H) X 480(V) PtSi focal plane array is presented. The 3 to 5 micron MWIR focal plane array supports interlaced, progressive scan, and subframe readout under control of on-chip digital decoders. The new design utilizes 1.25 micrometers design rules to achieve a 50% fill-factor, a noise equivalent delta temperature of <0.07 C (f/1.5, 30 Hz, 300 K), and a saturation level >1.5 X 106e. The power dissipation is less than 110 mW.

Performance of a high-frame-rate CCD imager

Back-illuminated, 16-port 512 X 512 and 32-port 1024 X 1024 charge coupled device (CCD) imagers have been fabricated. The measured performance of the 512 X 512 pixel chip is described, including data on quantum efficiency, dynamic range, dark current, frame rates, uniformity, contrast transfer function, and on-chip correlated double- sampling (CDS) amplifier noise. We have previously reported on these designs. The CCD arrays are designed with a unique combination of parameters optimized for applications requiring high resolution combined with high frame rates and wide dynamic range. The imaging registers achieve 100% optical fill factor and high quantum efficiency through the use of substrate thinning and back-side illumination. The high frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports which reduce the 512 X 512 array readout frequency to 15 MHz for 800 frame per second operation. On- chip CDS amplifiers are included in each output port to reduce the readout noise and simplify off-chip analog signal processing. Both designs include a buried anti-blooming drain structure and electro static discharge (ESD) protection.

Multiport backside-illuminated CCD imagers for high-frame-rate camera applications

Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.

Deep UV sensitive high frame rate backside illuminated CCD camera developments

New applications for ultra-violet imaging are emerging in the fields of drug discovery and industrial inspection. High throughput is critical for these applications where millions of drug combinations are analyzed in secondary screenings or high rate inspection of small feature sizes over large areas is required. Sarnoff demonstrated in1990 a back illuminated, 1024 X 1024, 18 um pixel, split-frame-transfer device running at > 150 frames per second with high sensitivity in the visible spectrum. Sarnoff designed, fabricated and delivered cameras based on these CCDs and is now extending this technology to devices with higher pixel counts and higher frame rates through CCD architectural enhancements. The high sensitivities obtained in the visible spectrum are being pushed into the deep UV to support these new medical and industrial inspection applications. Sarnoff has achieved measured quantum efficiencies > 55% at 193 nm, rising to 65% at 300 nm, and remaining almost constant out to 750 nm. Optimization of the sensitivity is being pursued to tailor the quantum efficiency for particular wavelengths. Characteristics of these high frame rate CCDs and cameras will be described and results will be presented demonstrating high UV sensitivity down to 150 nm.