Jinhyuck Yu

Design and Analysis of a Cascode Bipolar Low-Noise Amplifier With Capacitive Shunt Feedback Under Power-Constraint

A cascode bipolar low-noise amplifier (LNA) with capacitive shunt feedback has been developed to present a solution for simultaneous noise and power match when the real part of the optimum source impedance is not 50 Ω in order to keep high current density under power constraint. The proposed LNA also has the capability for the simultaneous improvement of noise figure (NF) and linearity. In addition, we analyzed and verified that the second-order interaction, which affects the third-order nonlinearity, becomes less sensitive to the low-frequency input termination at higher bias currents. The possibility of removing the low-frequency LC trap is investigated based on this analysis. We also show that LNAs with smaller base and/or smaller emitter resistances require lower source impedance at low frequencies to improve linearity by the same amount. Finally, prudent layouts for improving the performance of the LNA are considered. Eleven design examples of the proposed LNA, which individually operate at 880, 1575, or 1960 MHz, are fabricated in a low-cost 0.35- μm SiGe BiCMOS process to verify the design and analysis experimentally. The fabricated LNAs have excellent performances, especially in NF. For example, the 880-MHz LNA has an NF of 0.9 dB, a power gain of 16 dB, and an IIP3 of +14 dBm with current consumption of 11 mA from a 2.8-V power supply.

A direct conversion receiver with an IP2 calibrator for CDMA/PCS/GPS/AMPS applications

A second-order intercept point (IP2) calibration technique is developed using common-mode feedback (CMFB) circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/AMPS applications. The IP2 calibrator is capable of providing different CMFB gain to tune its common-mode output impedance for each of the positive and negative mixer outputs. The CDMA mixer applying this method achieved a second-order input intercept point (IIP2) of 64 dBm, a third-order input intercept point (IIP3) of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. This result shows a 20 dB improvement from an uncalibrated IIP2 of 44 dBm. The receiver RFIC is implemented in a 0.5-mum SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.

Design and analysis of a high-performance cascode bipolar low noise amplifier with shunt feedback capacitor

In this paper, a cascode bipolar low noise amplifier (LNA) employing a shunt feedback capacitor is presented, for which the linearity and the noise figure (NF) can be optimized by reducing the transistor size and degeneration inductance. We also show that the second-order interaction, which affects the third-order nonlinearity, becomes insensitive to low-frequency input termination as the DC current increases. Finally, the method of removing the low-frequency trap is presented. The fabricated LNA in 0.35-mum SiGe BiCMOS process showed NF of 0.9 dB with 16-dB power gain and IIP3 of +11 dBm with current consumption of 10 mA from 2.8-V power supply at 900 MHz. The demonstrated LNA satisfies stringent sensitivity and linearity requirement of code-division multiple-access (CDMA) applications quite well.

IP2 calibrator using common mode feedback circuitry

An IP2 calibration technique is developed using the common mode feedback circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/FM applications. The IP2 calibrator is capable of providing a different CMFB gain to tune its common mode output impedance for each of the positive and negative mixer outputs. The method performs a 20-dB improvement in IIP2. The CDMA mixer achieves an uncalibrated IIP2 of 44 dBm, an IIP3 of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. The receiver RFIC is implemented in a 0.5 /spl mu/m SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply. It exceeds all CDMA requirements when tested individually or on a handset.

A CMOS VCO with Optimized Tune Branches for Zero-IF CDMA Cellular Application in a 0.5μm BiCMOS process

A fully integrated, very-low phase-noise CMOS voltage controlled oscillator (VCO) has been implemented for zero-IF CDMA cellular receiver (Rx) using CMOS transistors in a 0.5mum SiGe BiCMOS process technology. To optimize the phase noise performance, the VCO used the proposed coarse and fine tune branch which employed high-Q accumulation-mode MOS (AMOS) varactors. The measured phase noise is below -133dBc/Hz at 900kHz offset frequency from a 1.762GHz carrier, which yields enough margin for the IS-98 single-tone test requirement. The integrated CDMA cellular Rx including this Rx VCO shows more than 2.5dB single-tone performance margin

A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOS

A fully integrated low-IF GPS receiver with minimum external components is implemented in a 65nm CMOS process. It has an integrated LNA and an active complex bandpass filter with a switchable signal bandwidth of 2MHz or 6 MHz to achieve the SNR improvement. To reduce power consumption, the current reusing method and current mode interface technique using a capacitive cross-coupled common-gate structure are applied. The measured noise figure of whole receiver including an external inter-stage SAW filter is 2.2dB. Its current consumption is 15mA at 1.8V supply.

A single-chip CDMA-2000 zero-IF transceiver for band-class 4 with GPS support

A single-chip cdma-2000 zero-IF transceiver has been successfully developed for band-class 4 (Korean-PCS band) with an additional GPS signal receiving functionality. The receiver showed excellent noise and linearity performance (full- path NF=2dB, IIP3=-6dBm) with very low phase-noise VCO (- 132dBc/Hz@1.25MHz/fOSC=3.71G). The Tx-Rx isolation turned out to be good enough for the sensitivity and single-tone desensitization requirement of the CDMA-2000 system. The IC was implemented on a 0.35mum SiGe BiCMOS technology.