Kun-Seok Lee

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

Phase frequency detectors for fast frequency acquisition in zero-dead-zone CPPLLs for mobile communication systems

This paper introduces a new-type phase-frequency-detector (PFD) for charge pump phase-locked-loops (CPPLLs). As the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property. The experimental results of the proposed PFD show the reduced frequency acquisition time by about 30% compared with the conventional PFD in the case of 70MHz voltage-controlled-oscillator (VCO) frequency hopping for PCS mobile applications. The PFD is designed and simulated by SPECTRE and the prototype, together with a frequency synthesizer, has been fabricated in a 0.5/spl mu/m BiCMOS technology.

VCO gain calibration technique for GSM/EDGE polar modulated transmitter

This paper describes a VCO gain calibration technique for the two-point modulation scheme using Delta-Sigma frequency synthesizer. The proposed technique enables PLL-based phase modulator to have wide bandwidth with good signal quality. A fully integrated GSM/EDGE polar modulated transmitter, implemented in a 0.13 mum CMOS process, is presented to show the feasibility of this calibration technique. After the calibration, it shows a margin of 8 dB to the spectrum mask at 400 kHz offset with EVM of 2%.

A Wideband 0.18-μm CMOS ΔΣ Fractional-N Frequency Synthesizer with a single VCO for DVB-T

This paper describes the design of the DeltaSigma fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receiver, which is fabricated in a 0.18-mum CMOS technology. A 3-bit 4th order sigma-delta (DeltaSigma ) modulator is employed for the fractional value implementation. A single on-chip voltage-controlled oscillator (VCO) covers a wideband frequency range- 900MHz to 1730MHz (63.1%) and provides the local oscillator (LO) signal - 470MHz to 862MHz via divider-2. The frequency synthesizer supports the whole channels and keeps the loop stable in operating and the performance variation is minimized over the wide frequency band. The variation of channel-to-channel switching time is also reduced. The measurement results show in-band phase noise is less than -80 dBc/Hz and out-of-band phase noise at 1.25 MHz offset is less than -128 dBc/Hz over all frequency range. The total lock time is less than 300 mus. The implemented frequency synthesizer consumes 10mA from 2.8-V power-supply

Fast AFC technique using a code estimation and binary search algorithm for wideband frequency synthesis

This paper presents some skills to improve locking property in wideband frequency synthesizers. To support a wide frequency range with a single on-chip voltage controlled oscillator (VCO) without deteriorating lock time, we introduce an adaptive frequency calibration (AFC) technique, which is using a code estimation and binary search algorithm to reduce the number of comparisons in AFC mode. In addition, by varying the threshold frequency, which is a criterion to discriminate one AFC code from others, in accordance with the requested VCO output frequency, the unnecessary transition time can be reduced during phase-locked loop (PLL) settling mode. A fractional-N frequency synthesizer with an on-chip LC VCO was implemented in 0.18-/spl mu/m CMOS technology to verify the performance. The measurement results showed less than 35-/spl mu/s AFC time with 5-bit AFC, and total lock time was found to be less than 65-/spl mu/s with 30 KHz PLL loop bandwidth. The frequency range was more than 400 MHz.

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate wideband frequency range, a switched capacitor bank LC tank VCO and an adaptive frequency calibration (AFC) technique are used. A 3-bit 4th order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3Hz as well as agile switching time. The experimental results show -80dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129dBc/Hz out-of-band phase noise at 400kHz-offset frequency. The fractional spurious is less than -70dBc/Hz at 300kHz offset frequency and the reference spur is -75dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

A 0.13-μm CMOS Σ-Δ frequency synthesizer with an area optimizing LPF, fast AFC time, and a wideband VCO for WCDMA/GSM/GPRS/EDGE applications

Use This paper presents a fully integrated fractional-N frequency synthesizer (FNFS) with an area optimizing low pass filter (LPF), fast adaptive frequency calibration (AFC) time, and a wideband on-chip LC voltage-controlled oscillator (VCO) for WCDMA/GSM/GPRS/EDGE transceivers. The FNFS employs a staked structure of MIM and MOS capacitors for LPF to economize the area. Fast AFC time is realized by using the prescaler output signal as a discriminating clock. A 3-bit 3rd order Sigma-Delta modulator serves as a fractional engine. Phase switching type prescaler is used to reduce the quantization noise of Sigma-Delta modulator. A fast switching CP is introduced. LC VCO utilizes bond-wire inductors with high Q-factor and a small area. Digitally controlled crystal oscillator (DCXO) provides a reference signal of high spectral purity. A prototype has been implemented in 0.13 mum CMOS technology. The measurements results show that the AFC time is less than 20-mus, in-band phase noise is -94 dBc/Hz, and out-band phase noise are -123 dBc/Hz at 400 KHz offset frequency and - 145 dBc/Hz at 3 MHz offset frequency when the carrier frequency is 900 MHz. Reference spur level is less than -75 dBc.

A /spl Sigma/-/spl Delta/ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver

This paper presents a fractional-N synthesizer with a 3-bit 4th-order interpolative /spl Sigma/-/spl Delta/ modulator for a GSM/GPRS direct conversion transceiver. With an integrated VCO and an integrated loop filter, the synthesizer achieves the phase noise performances less than -78dBc/Hz at close-in offset and less than -116dBc/Hz at 400kHz offset. The chip was fabricated and evaluated in a 0.35 /spl mu/m SiGe BiCMOS process.

A 3-bit 4/sup th/-order /spl Sigma/-/spl Delta/ modulator with metal-connected multipliers for fractional-N frequency synthesizer

This paper presents a 3-bit 4/sup th/-order /spl Sigma/-/spl Delta/ modulator for fractional-N frequency synthesizer. The modulator employs an interpolative architecture with multiple feedback paths and metal-connected multipliers to implement the feedback coefficients, resulting in a simple hardware complexity. A frequency synthesizer with the proposed modulator exhibits lower out-of-band phase noise, a frequency resolution of 6-Hz, and fast switching time. The experimental results show -82 dBc/Hz in-band phase noise and -140 dBc/Hz out-of-band phase noise at 1 MHz offset frequency. The fractional spurs are less than -80 dBc. A prototype has been implemented in 0.5-/spl mu/m BiCMOS technology.