Woon-kyung Lee

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

Thermal degradation of DRAM retention time: Characterization and improving techniques

Variation of DRAM retention time and reliability problem induced by thermal stress was investigated. Most of the DRAM cells revealed 2-state retention time with thermal stress. The effects of hydrogen annealing condition and fluorine implantation on the variation of retention time and reliability are discussed.

Analysis on data retention time of nano-scale DRAM and its prediction by probing the tail cell leakage current

Characteristics of the data retention time (tRET) of nano-scale DRAM have been described. In addition, new approaches to enhance tRET and their properties have been analyzed. To optimize the process, we developed the tRET-modeling methodology, which has a good agreement with experimental data. The key feature of the methodology is an indirect probing of the tail leakage current by fitting the leakage model to reproduce the measured characteristics of the retention. The model shows the GIDL current is a major factor determining tRET of 80nm RCAT technology.

Analysis of Thermal Variation of DRAM Retention Time

Variation of DRAM retention time induced by thermal stress was investigated. Thermal activation energies (Ea) of sub-threshold leakage, junction leakage and GIDL (Gate Induced Drain Leakage) current of a DRAM cell were measured using the test vehicles. The values were compared with Ea of 1/tREF for the DRAM cell of which the retention time had been varied after a thermal stress. Ea of 1/tREF for the thermally degraded DRAM cell was in the range of that for GIDL current, while Ea for the normal DRAM cells with high retention time was in the range of Ea for junction leakage. It is insisted that the thermal degradation of retention time is induced by increase in GIDL current. The contributions of gate oxide/substrate interface states to the GIDL current are discussed

Evaluation of STI degradation causing DRAM standby current failure in burn-in mode operation using a carrier injection method

P+ to p+ isolation degradation that causes DRAM standby current failure under burn-in mode operation is investigated. Although the isolation of the test devices dose not show any degradation or weakness in conventional electrical characterization, it is found that the degradation can be observed by a carrier injection method. Using the simple carrier injection method to simulate the real operating condition of a DRAM chip, a potential problem of the isolation degradation can be easily found, which cannot be screened by conventional electrical measurement.

New Cell Structure with Edge-thick Tunnel Oxide for Highly Reliable NAND Flash Memory Devices

One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is locally thin. For example, conventional SAP (self-aligned poly) process with shallow trench isolation, tunnel oxide at active edge is necessarily thinner than active channel. In this paper, we proposed a new process scheme to fabricate optimized tunnel oxide thickness varying from active center to edge, and we confirmed the improvement of reliability characteristics such as Vth shift and interface trap density during endurance cycling

Investigation of Hot carrier Degradation in Grooved Channel Structure nMOSFETs: Sphere shaped Recess Cell Array Transistor (SRCAT)

In this paper, first, it has been discussed hot carrier reliability in both Pch, RCAT and SRCAT. Second, we showed the origin of electric field suppression where the supply-voltage is applied at the same bias condition. Furthermore, we discuss the effects of ion implant process