Jeong-Hyuk Choi

Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS). The use of a high-k dielectric material, specially Al2O3, in the blocking oxide concentrates the electric fields across the tunnel oxide and SiN, and releases it across the blocking oxide under program and erase mode. This effect leads to lower program and erase voltage as well as faster erase speed than the conventional SiO2∕SiN∕SiO2 (SONOS) device. Moreover, it is shown that the fast erase operation is performed even at a thicker tunnel oxide over 30A where the hole direct tunneling current through the tunnel oxide is reduced significantly and thus the SANOS device has the excellent bake retention.

Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells

It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.

Intrinsic fluctuations in Vertical NAND flash memories

Vertical NAND (VNAND) technology relies on polysilicon for channel material. Two intrinsic variation sources of the cell threshold voltage induced by polysilicon traps have been identified and simulated: Random Trap Fluctuation (RTF) and Random Telegraph Noise (RTN). We demonstrate that RTN is enhanced by the polysilicon material and an original model explains the asymmetric RTN distribution observed after endurance. This work enables the prediction of VT distribution for VNAND devices in MLC operation.

Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells

We have verified that as the cell transistor width decreases below 100 nm for the NAND flash memory interface trap generation increases rapidly by FN current stress on the tunnel oxide. Accordingly, in contrast to the SILC (Stress-Induced Leakage Current) mechanism for the large dimensional cell transistors, it is revealed that the major failure mechanism of the data retention of 90 nm cell transistors is the relaxation of interface traps, which consist of the fast and slow traps. For the interface trap analysis, a new analysis method using I/sub d/-V/sub g/ hysteresis curve is proposed.

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

Todays explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.

New scaling limitation of the floating gate cell in NAND Flash Memory

As the scaling in NAND Flash Memory is progressed, the various interferences among the adjacent cells are more and more increased and the new phenomenon which is ignored until now has to be considered. In this paper, we will introduce the new program interference phenomenon which is generated between the program word line and the adjacent word lines along the bit-line. This new program interference is that the Vths of the adjacent word lines along the bit-line are decreased while a word line is programming. Because this phenomenon is severely aggravated as the gate space is decreased, we have to consider this program interference for the future technology nodes.

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, we succeed in developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest 128 Gb NAND Flash. The die size is 68.9 mm 2, program time is 700 us and I/O rate is 1 Gb/s.

A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology

A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.