Doris Dr Schmitt-Landsiedel

Hierarchical architecture for fast CMOS SRAMs

A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1- mu m technology yield a 9-ns access time for a 64 K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage.<<ETX>>

Design based failure analysis and yield improvement in CMOS‐circuits

In this paper we show that defect simulation is a basis for yield enhancement strategies. These strategies involve identification of the yield detractors (i.e. identification of spot defect characteristics) and yield oriented layout design, which uses information about defects. Information about key yield detractors can be obtained in a time and cost efficient manner using defect simulation. By comparison of process variants and of SRAMs with different layouts, the sensitivity of the method for process changes as well as for design differences is illustrated. This leads to the conclusion that the defect and yield simulation tools can be used for yield oriented design. The enormous cost and time savings demonstrated in this work give a signal to enforce the introduction of design based failure simulation methods into the yield learning process.

Automatic transistor sizing in high performance CMOS logic circuits

The authors present new methods for optimization-based automatic transistor sizing in digital CMOS VLSI circuits. The main novelty of their approach is that complete and accurate solutions of the circuit optimization problem are achieved at low computational costs. Hence complex design problems can be solved. As a practical application of the concepts, a circuit consisting of 11 logic gates is optimized. As a second example, the decoder of a hierarchical 64k-SRAM is considered, where parallel interacting signal paths are critical for timing. Noninferior design alternatives can be obtained by optimizing the different critical signal paths by successive application of the methods.<<ETX>>

Pipelined 16k Buffer RAM with 300MHz Operating Frequency

A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.