Gerd Neuendorf

Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits. >

Pipelined architecture for fast CMOS buffer RAMs

A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts. >

Hierarchical architecture for fast CMOS SRAMs

A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1- mu m technology yield a 9-ns access time for a 64 K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage.<<ETX>>

Automatic transistor sizing in high performance CMOS logic circuits

The authors present new methods for optimization-based automatic transistor sizing in digital CMOS VLSI circuits. The main novelty of their approach is that complete and accurate solutions of the circuit optimization problem are achieved at low computational costs. Hence complex design problems can be solved. As a practical application of the concepts, a circuit consisting of 11 logic gates is optimized. As a second example, the decoder of a hierarchical 64k-SRAM is considered, where parallel interacting signal paths are critical for timing. Noninferior design alternatives can be obtained by optimizing the different critical signal paths by successive application of the methods.<<ETX>>

Pipelined 16k Buffer RAM with 300MHz Operating Frequency

A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.