Dylan Kelly

Antenna impedance mismatch measurement and correction for adaptive CDMA transceivers

A tunable matching network has been developed to adaptively correct antenna impedance mismatch for CDMA transceivers. The tuning network consists of two L structures in cascade and is implemented with silicon-on-sapphire switches, fixed capacitors and inductors. Experimental results show the matching network can correct antenna impedance mismatch over a wide range. It has adequate linearity for CDMA applications and an insertion loss of 0.4 dB. A simple method has also been developed to measure the antenna load impedance based on the measurement of the envelope voltages at three points along a section of transmission line. This method is independent of input power to the antenna and source impedance seen by the antenna. This method could be integrated with the tunable matching network to correct the load impedance mismatch for an adaptive transceiver.

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc

Near zero turn-on voltage high-efficiency UHF RFID rectifier in silicon-on-sapphire CMOS

A UHF RFID rectifier which turns on at near zero input voltage is demonstrated. The rectifier is fabricated in 0.25-µm silicon-on-sapphire (SOS) CMOS technology using intrinsic, near zero threshold devices. A novel improved cross-coupled bridge topology is used to minimize the leakage incurred through the use of intrinsic devices while maintaining their low power turn on characteristics. The fabricated rectifier demonstrates a peak power conversion efficiency (PCE) of 71.5% at 915MHz with a RF input of −4 dBm and a 30 kΩ load. More importantly, a PCE ≫ 30% was measured for all RF input powers between −28 and −4 dBm demonstrating state-of-the-art efficiency across a wide range of input powers.

A

An inherent shortcoming of rectifiers designed using standard CMOS devices is poor low input power performance. It is shown that this can be overcome through the use of intrinsic devices with close to zero-threshold voltage available in a 0.25 μm silicon-on-sapphire (SOS) CMOS process. A novel complementary bridge rectifier structure based on a combination of cross-connected and diode bridge rectifier topologies is introduced to avoid the excessive leakage current incurred through the use of intrinsic devices. A design strategy which maximizes efficiency and produces an input impedance which will interface well with the inductive coil type antennas used in biomedical implants is presented for this new rectifier type. The fabricated rectifier achieves a 1 μW DC output power for an input power of -26.5 dBm at 100 MHz. A peak measured power conversion efficiency of 67% is achieved at 100 MHz, but more importantly >;30% PCE is attained for a wide output power range which reaches as low as -40 dBm. At the target 1 μW output power a PCE of 44% was achieved.

\mu

The explosion in the number of connected cellular devices and ever-increasing data bandwidth requirements has increased the number of bands a modern cellular device must support. This places stringent requirements on cellular handset antennas, as they need to cover more bands than ever before, while meeting increasing Total Radiated Power (TRP) requirements. A potential solution to this problem is achieved by the use of Tunable Matching Networks, which can maximize the transmitted radiated performance and receive sensitivity by optimizing the impedance match between the RF Front End and the Antenna. This paper outlines the challenging requirements placed on tunable components, presents a Tunable Matching Network utilizing Digitally Tunable Capacitors (DTCs), and proposes a method for evaluating the improvement this network brings to the cellular handset.

W Complementary Bridge Rectifier With Near Zero Turn-on Voltage in SOS CMOS for Wireless Power Supplies

The performance of spiral inductors on insulating substrates is far superior to ones fabricated in bulk CMOS or BiCMOS processes. In spite of this, SOI inductors are generally not satisfactory for very low noise or low insertion loss circuits. This work studies high frequency effects on current density in inductors and discusses improvements in metallization and layout. Based on this research, a 5.5 nH inductor has been fabricated on sapphire with a 540 um diameter and 4.5 um thick aluminum, resulting in a quality factor of 25 at 2 GHz.

CMOS based Tunable Matching Networks for cellular handset applications

This paper presents a CMOS envelope tracking power amplifier for LTE band-13 (782 MHz) applications. The envelope amplifier is implemented in 0.18 μm bulk CMOS process while the RF power amplifier is designed in 0.35 μm CMOS Silicon-on-Sapphire (SOS) technology. To overcome low breakdown voltage limit of MOSFETs, a stacked FET structure is used. The complete envelope tracking system achieves an overall PAE of 50% for 16 QAM, 10 MHz LTE signal with 6.6 dB peak-to-average ratio (PAPR), while delivering 29.3 dBm output power. A memory-less digital pre-distortion (DPD) is employed to linearize the overall system, which pushes ACLR down to -46.5 dBc.

Improvements to performance of spiral inductors on insulators

The deployment of LTE in the frequency range of 700 - 800 MHz is now occurring widely to support increased data application demands. Extending handset operation to lower frequencies in addition to existing bands results in up to 10 dB degradation of the radio link performance due to fixed matching networks. Solutions for tunability of the handset RF Front-End have been slow to develop, mainly attributed to the high operating voltages and wide tuning range requirements of the handset application. This paper outlines the requirements for handset RF Front-End tunability and presents a reconfigurable front-end impedance matching network utilizing digitally tunable capacitors (DTCs). Through the use of this tunable matching network, mismatch loss between the RFFE and the antenna can be reduced by up to 5dB.

An Envelope-Tracking CMOS-SOS Power Amplifier with 50% Overall PAE and 29.3 dBm Output Power for LTE Applications

Increased spectrum coverage by mobile wireless devices is dictating the need for active antenna systems. Silicon-on-Sapphire (SOS)-based Digitally Tunable Capacitors (DTCs) and switches enable tunable matching networks and dynamic adjustment of antenna electrical characteristics. Advancements in technology and design techniques have enabled improvements in DTC electrical performance. This paper addresses advancements in DTC and switch capabilities and the resulting improvements in antenna operating bandwidth.