E-Hung Chen

Power Optimized ADC-Based Serial Link Receiver

Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital signal post-processing has drawn growing interest with technology scaling, but power consumption remains among the key issues for such digital receiver in high speed applications. This paper presents an ADC-based receiver that uses a low-gain analog and mixed-mode pre-equalizer in conjunction with non-uniform reference levels for the ADC. The combination compensates for both the frontend non-ideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. The receiver is fabricated in a 65 nm CMOS technology with 10 Gb/s data rate, and has 13 pJ/bit and 10.6 pJ/bit power efficiency for a 29 dB and a 23 dB loss channel respectively.

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric

A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon the result of a single slicer, an efficient architecture named reduced-slicer partial-response DFE (RS-PRDFE) receiver is proposed. The RS-PRDFE receiver eliminates redundant or unused slicers from the previous DFE receiver implementations. Both the simulation and measurement results from a 10 Gb/s ADC-based receiver fabricated in 65 nm CMOS technology and multiple backplane channels demonstrate that the RS-PRDFE can achieve the BER of a 3-4-bit uniform ADC only with 4 data slicers. Also, the combined use of linear equalizers (LEs) can further reduce the required slicer count in RS-PRDFE receivers, but only when the LEs are realized in analog domain.

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.

ADC-based serial I/O receivers

Fully digital receiver frontends have garnered interest for serial I/O receivers. While the speed and resolution are achievable in CMOS technologies, the challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. This paper describes different design techniques and shows that the power can be reduced by constraining the specifications and by making architectural trade-offs.

Precursor ISI Reduction in High-Speed I/O

To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.

A 40-Gb/s serial link transceiver in 28-nm CMOS technology

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10-9. The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm2 per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm

This paper presents a low-power decision-feedback equalizer (DFE) receiver front-end and a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of 0.46 mW/Gbps is made possible by the combination of a direct-feedback finite-impulse-response (FIR) DFE, an infinite-impulse-response (IIR) DFE, and a clock-and-data recovery (CDR) circuit with adjustable timing offsets. Based on this architecture, the power-hungry stages used in prior DFE receivers such as the continuous-time linear equalizer (CTLE), the current-mode summing circuit for a multitap DFE, and the fast selection logic for a loop-unrolling DFE can all be removed. A two-step adaptation algorithm that finds the equalizer coefficients minimizing the BER is described. First, an extra data sampler with adjustable voltage and timing offsets measures the single-bit response (SBR) of the channel and coarsely tunes the initial coefficient values in the foreground. Next, the same circuit measures the eye-opening and bit-error rates and fine tunes the coefficients in background using a stochastic hill-climbing algorithm. A prototype DFE receiver fabricated in a 65-nm LP/RF CMOS dissipates 2.3 mW and demonstrates measured eye-opening values of 174 mV pp and 0.66 UIpp while operating at 5 Gb/s with a -15-dB loss channel.

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering

A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm2 and consumes 175 mW.

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS

The design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS is described. Accuracy requirements are met without compromising the high-speed performance by using trimming-based offset cancellation. The ADC can be configured to work as a 3-bit, a 4-bit, or a 5-bit ADC with maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.48LSB and 0.35LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv-step and the active area is 0.13 mm2.