Reza Navid

Comprehensive study of noise processes in electrode electrolyte interfaces

A general circuit model is derived for the electrical noise of electrode–electrolyte systems, with emphasis on its implications for electrochemical sensors. The noise power spectral densities associated with all noise sources introduced in the model are also analytically calculated. Current and voltage fluctuations in typical electrode–electrolyte systems are demonstrated to originate from either thermal equilibrium noise created by conductors, or nonequilibrium excess noise caused by charge transfer processes produced by electrochemical interactions. The power spectral density of the thermal equilibrium noise is predicted using the fluctuation-dissipation theorem of thermodynamics, while the excess noise is assessed in view of charge transfer kinetics, along with mass transfer processes in the electrode proximity. The presented noise model not only explains previously reported noise spectral densities such as thermal noise in sensing electrodes, shot noise in electrochemical batteries, and 1/f noise in corrosive interfaces, it also provides design-oriented insight into the fabrication of low-noise micro- and nanoelectrochemical sensors.

Minimum achievable phase noise of RC oscillators

To make RC oscillators suitable for RF applications, their typically poor phase-noise characteristics must be improved. We show that, for a given power consumption, this improvement is fundamentally limited by the fluctuation-dissipation theorem of thermodynamics. We also present the analytical formulation of this limit for relaxation (including ring) oscillators using a time-domain phase-noise analysis method which is introduced in this paper. Measurement shows the maximum possible improvement is generally less than 6dB for ring oscillators, while it can be as high as 21dB for other relaxation oscillators. The suboptimal performance of relaxation oscillators is attributed to the continuous current flow in these oscillator topologies. These results provide useful insight for feasibility studies of oscillator design.

Biological shot-noise and quantum-limited signal-to-noise ratio in affinity-based biosensors

We study the statistical behavior of affinity-based biosensors. The detection uncertainty and noise in such devices originates primarily from probabilistic molecular-level bindings within the sensing regions, and the stochastic mass-transfer processes within the reaction chamber. In this paper, we model the dynamic behavior of these sensory systems by a Markov process, which enables us to estimate the sensor inherent noise power spectral density (PSD) and response time. We also present the methods by which the Markov parameters are extracted from the reaction kinetic rates, diffusion coefficients, and reaction chamber boundary conditions. Using this model, we explain why Poisson shot noise has been reported in such biosensors and additionally predict a Lorentzian profile for the fluctuation PSD. Furthermore, we demonstrate that affinity-based biosensors have a quantum-limited signal-to-noise ratio (SNR). We also show that the SNR decreases as the dimensions are isomorphically scaled down while the biosens...

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40 nm DRAM process that has a fan-out of four-inverter delay (FO4) of 45 ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380 fs rms at the transmitter output and BER <10-14 while consuming 8 mW/Gb/s.

The physical phenomena responsible for excess noise in short-channel MOS devices

The physical phenomena responsible for the excess noise in short-channel MOS devices are explained based on the non-equilibrium noise theory. Comparing the MOS excess noise with the well known excess noise in a mesoscopic conductor, it is suggested that the physical origins of both are the same. Using this theory, it is proposed that the noise sources used in the impedance field method (IFM) should contain not only the usual thermal noise component, but also a partially suppressed shot noise term which accounts for the limited number of inelastic scattering events in the channel. The theoretical predictions of a simplified model based on this theory are presented and compared with the measurement results. It is shown both theoretically and experimentally that the non-equilibrium noise component is smaller when a larger gate to source voltage is applied. The accurate calculation of the suppression factor, which is in general a function of device terminal voltages, remains a challenge.

High-frequency noise in nanoscale metal oxide semiconductor field effect transistors

The noise characteristics of today’s short-channel devices are shown to have a better resemblance to ballistic devices than to long-channel metal oxide semiconductor field effect transistors (MOSFETs). Therefore the noise characteristics of these devices are best modeled using a ballistic-MOSFET-based noise model. Extensive hydrodynamic device simulations are presented in support of this hypothesis and a simple compact model is introduced. This model is used for predicting the noise behavior of future nanoscale devices. Most of the findings of this work can also be applied to carbon nanotubes and nanowires because of their similarities to MOSFETs.

An analytical formulation of phase noise of signals with Gaussian-distributed jitter

The output of many oscillatory systems can be approximated by a stochastic square-wave signal with noise-free amplitude and Gaussian-distributed jitter. We present an analytical treatment of the phase noise of this signal with white and Lorentzian jitter spectra. With a white jitter spectrum, the phase noise is nearly Lorentzian around each harmonic. With a Lorentzian jitter spectrum, it is a sum of several Lorentzian spectra, a summation that has a 1/f/sup 4/ shape at far-out frequencies. With a combination of the two, it has 1/f/sup 4/ and 1/f/sup 2/ shapes at close-in and far-out frequencies, respectively. In all cases, the phase noise at the center frequency and the total signal power are both finite. These findings will improve our understanding of phase noise and will facilitate the calculation of phase noise using time- domain jitter analysis.

A 40-Gb/s serial link transceiver in 28-nm CMOS technology

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10-9. The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm2 per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

A fast-wakeup bang-bang LC digital phase-locked loop (DPLL) suitable for low-power wireline applications is presented. The PLL uses a novel oscillator design to generate eight output phases using magnetic coupling. The fast-wakeup feature improves power efficiency by allowing PLL power-cycling while accommodating latency requirements. Fast lock upon wakeup is achieved by calibrating the phase of the feedback clock with respect to the reference clock using a first-order loop and is further assisted by on-the-fly adjustment of loop parameters. The eight-phase output clock is generated using a loop of four digitally-controlled oscillators (DCOs) that are magnetically coupled through a passive structure. This structure enables magnetic coupling among oscillators with 2x area improvement over the prior art. As a result, in addition to eliminating the noise and parasitic capacitance of active coupling devices, the compact design reduces parasitic wiring capacitance, which is a significant limitation in high-frequency coupled oscillator design. Implemented in a 40 nm CMOS technology, the design achieves a 40-reference-cycle (100 ns) lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° quadrature phase error up to 25 GHz. Measured PLL jitter is 392 fs (integrated from 100 kHz to 100 MHz) at 25 GHz while drawing 64 mW of power, 23 mW of which is consumed in the multiphase DCO. The DPLL occupies a total area of 0.1 mm2.