P.-Y. Chan

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx-cladded Si or GeOx-cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx-cladded Si or GeOx-cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx-cladded Si and GeOx-cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (ID–VG) shows four-state behavior with two intermediate states between the conventional ON and OFF states.

Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator

An indium gallium arsenide quantum-dot-gate field-effect transistor using Zn0.95Mg0.05S as the gate insulator is presented in this paper, showing three output states which can be used in multibit logic applications. The spatial wavefunction switching effect in this transistor has been investigated, and modeling simulations have shown supporting evidence that additional output states can be achieved in one transistor.

Quantum Dot Channel (QDC) Field Effect Transistors (FETs) and Floating Gate Nonvolatile Memory Cells

This paper presents silicon quantum dot channel (QDC) field effect transistors (FETs) and floating gate nonvolatile memory structures. The QDC-FET operation is explained by carrier transport in narrow mini-energy bands which are manifested in an array of SiOx-cladded silicon quantum dot layers. For nonvolatile memory structures, simulations of electron charge densities in the floating quantum dot layers are presented. Experimental threshold voltage shift in ID–VG characteristics is presented after the ‘Write’ cycle. The QDC-FETs and nonvolatile memory due to improved threshold voltage variations by incorporating the lattice-matched II–VI layer as the gate insulator.

Multi-Bit Quantum Dot Nonvolatile Memory (QDNVM) Using Cladded Germanium and Silicon Quantum Dots

In this paper, we are experimentally demonstrating the multi-bit storage of a nonvolatile memory device with cladded quantum dots as the floating gate. These quantum dot nonvolatile memory (QDNVM) devices were fabricated by using standard complementary metal-oxide-semiconductor (CMOS) process. The quantum dots in the floating gate region assembled using site-specific selfassembly (SSA) technique. Quantum mechanical simulations of this device structure are also presented. The experimental results show that the voltage separation between the bits was 0.15V and the voltage pulses required to write these bits were 11.7V and 30V. These devices demonstrated the larger write voltage separation between the bits.

Automatic door opener

People may have difficulty accessing the entry door to their house because it is difficult for them to turn a key or they cannot maneuver a wheelchair into a position to either open the door or grasp the doorknob. The Automatic Door Opener is designed to pneumatically open or close a door by remote control using radio frequency communication technology. A fingerprint recognition system is also installed for security purposes preventing unauthorized users from gaining entry.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeOx-cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Quantum Dot Channel (QDC) Field Effect Transistors (FETs) Configured as Floating Gate Nonvolatile Memories (NVMs)

This paper presents quantum dot channel (QDC) Field Effect Transistors (FETs) which are configured as nonvolatile memories (NVMs) by incorporating cladded GeOx-Ge quantum dots in the floating gates as well as the transport channels. The current flow and the threshold characteristics were significantly improved when the gate dielectric was changed from silicon dioxide (SiO2) to hafnium aluminum oxide (HfAlO2), and the control dielectric was changed from silicon nitride (Si3N4) to hafnium aluminum oxide (HfAlO2). The device operations are explained by carrier transport in narrow energy mini-bands which are manifested in a quantum dot transport channel.