B. Miller

SPATIAL WAVEFUNCTION-SWITCHED (SWS)-FET: A NOVEL DEVICE TO PROCESS MULTIPLE BITS SIMULTANEOUSLY WITH SUB-PICOSECOND DELAYS

Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx-cladded Si or GeOx-cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.

Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator

An indium gallium arsenide quantum-dot-gate field-effect transistor using Zn0.95Mg0.05S as the gate insulator is presented in this paper, showing three output states which can be used in multibit logic applications. The spatial wavefunction switching effect in this transistor has been investigated, and modeling simulations have shown supporting evidence that additional output states can be achieved in one transistor.

Four-state FETs incorporating quantum dot gate (QDG), quantum dot channel (QDC) and spatial wavefunction-switched (SWS) structures: Basis for 2-bit processing circuit architectures

Three-state behavior has been demonstrated in Si and InGaAs FETs when two layers of cladded nanodots (e.g. SiOx-cladded Si or GeOx-cladded Ge) are assembled on the thin tunnel gate insulator. The advantages of 3-state behavior in reducing device count in logic, analog-to-digital converters (ADCs), and DACs has been reported [1]. Unlike three-state QDG-FETs, four-state devices offer significant advantages in reducing device count and power dissipation in multi-valued logic architecture.

3-State behavior in quantum dot gate FETs

Quantum dot (QD) gate Si FETs, exhibiting an intermediate state “i” in their transfer characteristics, were first reported in ISDRS-07 [1]. The “i” state is characterized by a low-current saturation behavior which occurs in a range of gate voltage. Its origin is attributed to the transfer of charge from the inversion channel to the either one of the two cladded quantum dot (e.g. SiOx-Si) layers assembled in the gate region over the thin gate insulator [1,2]. The tunneling of charge from the inversion layer to the first layer of Si quantum dots (and their eventual transfer to the second layer of Si quantum dots via resonant tunneling as the gate voltage is increased) results in an increase the threshold voltage. The variation of the threshold voltage due to compensation of the gate insulator charge results in a low current saturation “i” state.