M. Gogna

Fabrication and Circuit Modeling of NMOS Inverter Basedon Quantum Dot Gate Field-Effect Transistors

This paper presents the fabrication of a negative-channel metal–oxide–semiconductor (NMOS) inverter based on quantum dot gate field-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, predicting the fabricated device characteristic.

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

Application of quantum dot gate nonvolatile memory (QDNVM) in image segmentation

This paper presents the application of quantum dot gate nonvolatile memory (QDNVM) in image processing application. The charge accumulation in the gate region varies the threshold voltage of QDNVM, which can be used as a reference voltage source in a comparator circuit. A simplified comparator circuit can be implemented using the QDNVM. In this work, the use of QDNVM-based comparators in image processing specially image segmentation is demonstrated, which can be efficient in future image processing application.

Fabrication and Simulation of InGaAs Field-Effect Transistors with II-VI Tunneling Insulators

This study shows the use of a high-κ ZnS/ZnMgS/ZnS heteroepitaxial tunneling layer in an InGaAs field-effect transistor. Experimental fabrication and simulation of this semiconductor structure show promise of reducing threshold voltage variation by replacing silicon and hafnium oxides as a gate insulator. The II–VI tunneling insulator is grown on an InGaAs substrate using ultraviolet-irradiated metalorganic vapor-phase epitaxy. GeOx-Ge cladded quantum dots are self-assembled to form the gate material. The gate consists of two self-assembled individually cladded quantum dot layers which allow multilogic behavior. Simulations calculated by solving the Schrödinger and Poisson equations self-consistently confirm experimental ID–VD characteristics and show the electron distribution in an inversion channel/quantum well under different gate voltage bias values.

ZNS/ZNMGSETE/ZNS II-VI Energy Barrier for INGAAS Substrates

InGaAs high mobility transistors presently provide the fastest speeds. As InGaAs nonvolatile memory field effect transistors (NVMFETs) are scaled down past 22 nm gate width, threshold voltage variation becomes a limiting factor. Replacing the amorphous SiO2 or HfO2 with a heteroepitaxial barrier stack the threshold voltage can be stabilized by minimizing the interface charge at the barrier-channel interface. The floating gate is comprised of individually germanium-oxide cladded germanium quantum dots. The tunneling layer is comprised of a quantum well stack of ZnSe/ZnS/ZnMgSeTe/ZnS/ZnSe. The magnesium incorporation increases the the energy barrier but introduces dislocation that can leak charge. The ZnS and ZnSe layers have a lower bandgap but a lower dislocation density to assist with gate leakage prevention. We present simulation and experimental C-V data on InGaAs FET and II-VI tunneling layer on an InGaAs substrate respectively.

3-State behavior in quantum dot gate FETs

Quantum dot (QD) gate Si FETs, exhibiting an intermediate state “i” in their transfer characteristics, were first reported in ISDRS-07 [1]. The “i” state is characterized by a low-current saturation behavior which occurs in a range of gate voltage. Its origin is attributed to the transfer of charge from the inversion channel to the either one of the two cladded quantum dot (e.g. SiOx-Si) layers assembled in the gate region over the thin gate insulator [1,2]. The tunneling of charge from the inversion layer to the first layer of Si quantum dots (and their eventual transfer to the second layer of Si quantum dots via resonant tunneling as the gate voltage is increased) results in an increase the threshold voltage. The variation of the threshold voltage due to compensation of the gate insulator charge results in a low current saturation “i” state.