Supriya Karmakar

Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.

Design of ADCs and DACs using 3-state quantum DOT gate FETs

This paper presents the circuit model of 3-state quantum dot gate FETs and design of three bit Analog to Digital Converter (ADC) and Digital to Analog (DAC) converter based on that model.

Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs

The spatial wave-function switched field-effect transistor (SWSFET) has two or three low bandgap quantum well channels that can conduct carrier flow from source to drain of the SWSFET. Because of this property, SWSFETs are useful to implement different multivalued logic with reduced device count. In this paper, we introduce the circuit model of a SWSFET and the design of a unipolar inverter where only one kind of charge carrier contributes to the current flow. We also simulate two input unipolar logic gates such as NAND and NOR and demonstrate their universal property to implement other unipolar logic gates. We also simulate NOR gate and full adder circuits based on unipolar logic gates.

Implementation of Six Bit ADC and DAC Using Quantum Dot Gate Non-Volatile Memory

This paper presents the implementation of six-bit analog to digital converters (ADCs) and digital-to-analog converters (DACs) using quantum dot gate non-volatile memory (QDNVM). The charge accumulation in the gate region varies the threshold voltage of QDNVM which can be used as a reference voltage source in a comparator circuit. A simplified comparator circuit can be implemented using the quantum dot gate non-volatile memory (QDNVM). In this work, we discuss the use of QDNVM based comparators in designing 6-bit Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs).

Design of four-state inverter based on spatial wave-function switched FETs

A spatial wave-function switched field effect transistor (SWSFET) conducts current from the source to the drain region through different channels inside the FET based on the applied gate voltage. A circuit model of SWSFET is developed by modifying Berkeley short-channel IGFET model (BSIM 3.2.0), and a four-state inverter is designed based on that model. This four-state inverter may become a key element in future quaternary logic circuit design.

Implementation of Membership Function using Spatial Wave-Function Switched FETs

Spatial wave-function switched field effect transistor (SWSFET) switches the current flow between different channels inside the FET based on the applied voltage in its gate terminal. SWSFET can be used to implement multi-valued logic circuit with less number of circuit elements. Recently we presented unipolar inverter circuit using SWSFET. In this paper we develop a circuit model of SWSFET based on BSIM 3.2.0 and BSIM 3.2.4 and implement membership function using that circuit model of SWSFET. The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the SWSFET, switches the charge carrier concentration in different channels from source to drain region. A circuit model of SWSFET is developed in BSIM 3.2.0. Membership function is implemented using the circuit model of the SWSFET. Membership function implementation using less number of SWSFET will reduce the device co...

Eight bits ADC using non-volatile flash memory

Analogue-to-digital converter (ADC) is a very important circuit element to convert analogue signal into digital signal for information processing. There are several designs to implement ADC. The precision of an ADC depends on its resolution. In this work, this group has shown the design of eight-bit ADC using quantum dot gate non-volatile memory (QDNVM). The controllable threshold voltage of QDNVM is very useful to design comparators which are the main component of this ADC circuit. This work shows the use of QDNVM in eight-bit ADC design.

Four-state FETs incorporating quantum dot gate (QDG), quantum dot channel (QDC) and spatial wavefunction-switched (SWS) structures: Basis for 2-bit processing circuit architectures

Three-state behavior has been demonstrated in Si and InGaAs FETs when two layers of cladded nanodots (e.g. SiOx-cladded Si or GeOx-cladded Ge) are assembled on the thin tunnel gate insulator. The advantages of 3-state behavior in reducing device count in logic, analog-to-digital converters (ADCs), and DACs has been reported [1]. Unlike three-state QDG-FETs, four-state devices offer significant advantages in reducing device count and power dissipation in multi-valued logic architecture.

3-State behavior in quantum dot gate FETs

Quantum dot (QD) gate Si FETs, exhibiting an intermediate state “i” in their transfer characteristics, were first reported in ISDRS-07 [1]. The “i” state is characterized by a low-current saturation behavior which occurs in a range of gate voltage. Its origin is attributed to the transfer of charge from the inversion channel to the either one of the two cladded quantum dot (e.g. SiOx-Si) layers assembled in the gate region over the thin gate insulator [1,2]. The tunneling of charge from the inversion layer to the first layer of Si quantum dots (and their eventual transfer to the second layer of Si quantum dots via resonant tunneling as the gate voltage is increased) results in an increase the threshold voltage. The variation of the threshold voltage due to compensation of the gate insulator charge results in a low current saturation “i” state.