Stéphane Meillère

A temperature compensated CMOS ring oscillator for wireless sensing applications

This paper presents a CMOS voltage controlled ring oscillator (VCO) with temperature compensation circuit suitable for low-cost and low-power wireless sensing applications. To operate at low frequency, a control voltage generated by a CMOS bandgap reference (BGR) is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 1V. The chip is fabricated in AMS 0.35 µm CMOS process with an area of 0.032mm2. Operating at 1.25V, the output frequency is within 200±l0kHz over the temperature range of −25°C to 80°C with power consumption of 810µW.

A low power consumption CMOS differential-ring VCO for a Wireless Sensor

This paper describes a three-stage Voltage Controlled ring Oscillator (VCO) based on 0.35 μm CMOS standard technology. The VCO was designed for a transmitter operating in the 863–870 MHz European band for Wireless Sensor applications. A voltage VCTRL controls the oscillation frequency of the VCO. Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 3.3 V, is only 7.48 mW. The proposed VCO exhibits a phase noise lower than −126 dBc/Hz at 10 MHz offset frequency.

Single ended rail-to-rail CMOS OTA based variable-frequency ring-oscillator

A new current-controlled ring oscillator based on a single-ended rail-to-rail operational transconductance amplifier (OTA) and three simple CMOS inverters is presented in this paper. The tuning frequency of the proposed oscillator is achieved by modifying the OTA DC bias current. Our proposed CMOS oscillator has been simulated under 3.5 V with the 0.8 /spl mu/m BiCMOS technology from AMS. For a DC bias current between 1 /spl mu/A to 200 /spl mu/A, simulation results confirm wide tuning range of 1.2 MHz to 36 MHz. The total circuit area is only 0.05 mm/sup 2/.

A 4GHz CMOS 130 nm IR-UWB dual front-end transceiver for IEEE802.15 standards

A single chip CMOS 130 nm transceiver for UWB-IR communications was assembled and measured for further integration into a demonstrator aiming compatibility with the recently published IEEE802.15.6 standard for Body Area Networks. The transmitter achieves a 10.9 mA current consumption for the 15.6MHz pulse repetition frequency and 1.5V peak-to-peak voltage. The receiver is an innovative combination of a low current consumption non coherent envelop detector and of a high sensitivity coherent quadrature demodulator. Different compromises in sensitivity, current consumption and acquisition speed are made possible. This paper briefly describes the architecture and provides the chip measurement results.

Transconductance CMOS inverter based AC coupling amplifier

An AC-coupling technique based on the complementary MOS inverter is presented in this paper. The proposed technique employs a coupling capacitance, a reference inverter and two transistors in resistive mode of operation. As an application, a threes stage amplifier has been realized in 0.35μm CMOS process. Under 2.5V supply voltage, the amplifier features a 23.6dB measured voltage gain. At the same measurement condition, the total power consumption is lower than 295μW and the amplifier exhibits a total harmonic distortion of 3% when the peak-to-peak output voltage swing is 750mV.

Combiners based on CMOS inverters and application in RF transmitter for wireless sensors

A new Combiner architecture for direct conversion transmitter based on CMOS inverters only and operating in transconductance mode is presented in this paper. Typical applications of an adder and a subtractor of two small amplitude signals are proposed to illustrate the circuit capabilities. The proposed circuit operation has been acted from measurements with the HCC/HCF4069UB Hex Inverter from the SGS Thomson Microelectronics [1].

OOK/NCP-FSK modulator based on coupled open-closed-loop VCOs

In this paper a simple FSK/OOK modulator based on a proposed CMOS coupled voltage controlled oscillators is presented. In FSK mode the circuit is a non-continuous phase FSK (NCPFSK) which exhibits a relatively low phase discontinuity at the frequency transition times. The proposed modulator is built from CMOS inverters. The circuit is self biased and the frequency of oscillations can be easily shifted by opening and closing the open loop of each oscillators. Regarding technology, the modulator, which uses any active inductor, is able to operate at high frequency and provides digital output with suitable phase noise. Simulation result from typical parameters of a 0.35 mum CMOS Process is given. The circuit functioning has been also acted from measurements completed from prototypes fabricated with HFE4069 from Philips Semiconductor [1].

A simple clock-fault detection analog circuit for high-speed crystal oscillators

This paper presents a simple architecture for clock-fault detection in high-speed applications. The overall principle consists in converting a possible error of time to a logic voltage level. When a high voltage level is present at the output, a reliable clock is detected whereas a low voltage level implies a clock error. This detection system is intended for all System-on-Chip such as microcontrollers which use external clock from 4 MHz to 50 MHz. The proposed circuit is realized in CMOS 40 nm process technology. Simulation results prove the suitability of the structure and its integration on silicon is strongly considered by clock error detection in integrated circuits.

Investigation on bond wire dedicated to integrated time base

This paper presents an investigation work about the bond wire electrical performances, with the aim of designing an integrated time base using the bond wire inductance. Our work was focused on the characterization of single and double gold bond wire, and multi bond wire length for the frequency range from 500 MHz to 5 GHz. A lumped n-model is used for the modeling and the electrical parameters are extracted thanks to the measured S-parameters. A de-embedding procedure is performed to characterize the bond wire. Finally, a structure is proposed to employ the bond wire into an integrated time base.

Analysis of the IEEE 802.15.4a UWB PHY layer for optimizing the power consumption of the transmitter

This paper presents an analysis of the power consumption of the UWB PHY layer of the IEEE 802.15.4a standard. This work focuses on the transmitter PHY layer implementation. The influence of the different modes settings on the power consumption is investigated. The considered implementations use an FPGA coupled with an UWB pulse generator implemented in an ASIC. The first PHY layer implementation is fully integrated in the FPGA. The consumption study reveals that the system consumption is reduced with the Mean PRF of 3.9 MHz due to the lower number of emitted pulses. The study also shows that the highest power consumption is due to the 499.2 MHz clock. The second implementation proposes to move the 499.2 MHz clock into the ASIC to reduce its consumption. For the mandatory data rate and the 3.9 MHz Mean PRF, this technique reduces the energy by emitted bit from 2574 pJ to 727 pJ.