Thomas E. Lombardi

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.

Effect of Underfill Formulation on Large-Die, Flip-Chip Organic Package Reliability: A Systematic Study on Compositional and Assembly Process Variations

Selection of appropriate underfills (or encapsulants) for flip-chip packages is critical to their reliability. In this research article, we present a comprehensive study geared towards the development of such materials. Several underfill formulations were developed based on the target material property guidelines obtained from parametric numerical simulations. Material parameters such as base resin composition, filler particle size, filler particle surface treatment and adhesive strength were modulated to arrive at an optimal composite material composition which facilitated package assembly. The robustness of these formulations was further evaluated by conducting post-assembly thermal cycling tests. Results on the reliability performance of these tailor-made underfills along with the failure analysis studies and correlation with numerical modeling will be presented.

Finite Element Modeling of C4 Cracking in a Large Die Large Laminate Coreless Flip Chip Package

BGA substrates made of organic materials are now industry standard as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. A typical organic laminate structure consists of one or more layers of build-up and copper on each side of a copper clad core. In recent years, the industry has also introduced the concept of organic build up laminate without a core layer, more commonly known as coreless laminates, to overcome the disadvantages of the plated through holes (PTH) in the core structures, which specifically drive restrictions in wiring capability and retard signal transmission speed. Although coreless laminates offer better opportunity for low cost and high speed transmission package designs, they are usually associated with high thermal warpage due to the lack of reinforcement provided by a rigid core layer. This becomes particularly challenging in large body size substrates. Furthermore, the composite coefficient of thermal expansion (CTE) of a coreless laminate is significantly higher than cored alternatives, which leads to higher chip package interaction (CPI) stresses. This paper focuses on the reliability issues of C4 bump cracking in a large die large laminate (LDLL) coreless flip chip package. C4 solder bumps are subjected to shear strains and fatigue degradation during thermal cycling and power cycling in field operation. Such shear strain is normally proportional to the DNP (distance from neutral point). Therefore solder fatigue often occurs at the corner C4s first. To further increase the reliability concern, the composite CTEs of coreless organic laminates are higher than cored laminates, which impose additional shear strain to the C4 interconnect bumps. Two coreless flip chip packages, with pad defined C4 bumps and solder mask opening defined C4 bumps, will be examined in this paper. Comparison of fail counts after 1000 cycles of deep thermal cycling (DTC) reveals that pad defined C4 bumps are more robust than solder mask opening defined C4s. Failure analysis of the cracked C4 bumps will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. Parametric studies on the effect of C4 bump geometry, laminate material properties and other form factors on C4 fatigue will be discussed. A predictive model for C4 solder joint fatigue in coreless flip chip packages will be proposed.