Charles L. Reynolds

Development of a Low CTE chip scale package

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.

Inspection/metrology benchmarking on fine pitch design substrate for advanced packages

Integrated silicon packages, such as System in Package, are becoming more popular as electronic packaging solutions, and this technology is driving the need for finer and finer circuit pattern designs. However, optical inspection methodologies are reaching their limits in detecting defects efficiently at these smaller dimensions. This potential technology gap could negatively impact yield performance and quality validation of the substrates or boards used for integrated SiP packages. The lack of inspection capability for fine lines and spaces on panel size substrates and boards used to fabricate SiP carriers supporting high I/O or high bandwidth memory or other components could have a negative impact on yield performance or reliability. This issue has been defined as a technical gap less than “15μm/15μm line space” design rules in the iNEMI package roadmap. iNEMI conducted an industry survey to assess the measurement and inspection capability for fine circuit pattern substrates with features less than 15μms used in high bandwidth applications. The survey is conducted across the entire electronic supply chain from substrate manufacturers to inspection equipment manufacturers, and covers the aspects of product quality and reliability, material and processing, inspection capability, analysis techniques and data management. This paper discusses the findings obtained from the survey results and makes recommendations on metrology capabilities that are required to close the technical gap, with respect to product requirements and process and material capabilities.

A high performance Multi Component Carrier with Chip Scale Package

In this paper, we discuss the design of a four (4) chip Multi Component Carrier (MCC) package and feasibility for use in high-end server/mainframe applications. A new class of organic, Chip Scale Package (CSP) and associated design ground rules were created based on a low, coefficient of thermal expansion (CTE) organic material, in addition to the CSP form factor. Micro Ball Grid Array (BGA) is used to connect the CSP to a daughter card assembly to form the MCC package structure. The low CTE organic substrate significantly reduces the internal stress that arises from the chip to substrate bond and assembly process, which enhances the yield and reliability of the CSP and the entire MCC structure. Numerical simulation using the finite element method (FEM) has been conducted to evaluate and optimize the lid design of the MCC package in order to ensure reliable lid to package operation during assembly and field thermal excursions. Thermal and mechanical solutions with various combinations of geometric design are discussed.

Finite Element Modeling of C4 Cracking in a Large Die Large Laminate Coreless Flip Chip Package

BGA substrates made of organic materials are now industry standard as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. A typical organic laminate structure consists of one or more layers of build-up and copper on each side of a copper clad core. In recent years, the industry has also introduced the concept of organic build up laminate without a core layer, more commonly known as coreless laminates, to overcome the disadvantages of the plated through holes (PTH) in the core structures, which specifically drive restrictions in wiring capability and retard signal transmission speed. Although coreless laminates offer better opportunity for low cost and high speed transmission package designs, they are usually associated with high thermal warpage due to the lack of reinforcement provided by a rigid core layer. This becomes particularly challenging in large body size substrates. Furthermore, the composite coefficient of thermal expansion (CTE) of a coreless laminate is significantly higher than cored alternatives, which leads to higher chip package interaction (CPI) stresses. This paper focuses on the reliability issues of C4 bump cracking in a large die large laminate (LDLL) coreless flip chip package. C4 solder bumps are subjected to shear strains and fatigue degradation during thermal cycling and power cycling in field operation. Such shear strain is normally proportional to the DNP (distance from neutral point). Therefore solder fatigue often occurs at the corner C4s first. To further increase the reliability concern, the composite CTEs of coreless organic laminates are higher than cored laminates, which impose additional shear strain to the C4 interconnect bumps. Two coreless flip chip packages, with pad defined C4 bumps and solder mask opening defined C4 bumps, will be examined in this paper. Comparison of fail counts after 1000 cycles of deep thermal cycling (DTC) reveals that pad defined C4 bumps are more robust than solder mask opening defined C4s. Failure analysis of the cracked C4 bumps will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. Parametric studies on the effect of C4 bump geometry, laminate material properties and other form factors on C4 fatigue will be discussed. A predictive model for C4 solder joint fatigue in coreless flip chip packages will be proposed.