Edward R. Pillai

Coax via-A technique to reduce crosstalk and enhance impedance match at vias in high-frequency multilayer packages verified by FDTD and MoM modeling

Large-scale crosstalk at vias and poor via electrical performance are major drawbacks in state-of-the-art high-frequency multilayer first- or second-level integrated-circuit/monolithic-microwave integrated-circuit (IC/MMIC) packages. The coax via design modeled in this paper breaks new ground in achieving more than 30-dB ultrawide-band crosstalk reduction and providing an enhanced impedance match.

Novel T-Coil Structure and Implementation in a 6.4-Gb/s CMOS Receiver to Meet Return Loss Specifications

A wide range of serializer deserializer (SerDes) Compliance Specifications exist for the Return Loss seen at the Package interface to the printed circuit board (PCB) for High Speed Links. For the goal of achieving interoperability it is expected that the most stringent Return Loss specification is met. The Return Loss performance is also an indication of available Chip and package bandwidth (BW). This paper demonstrates the use of a T-Coil (two series connected inductors with a center tap) in a 90 nm process CMOS SerDes Receiver to enable the Chip and Package to meet the Return Loss specification and in addition extend the usable BW.