Eero Ivask

Internet-Based Collaborative Test Generation with MOSCITO

This paper offers an Internet-based environment for enhancing problem-specific design flows with test pattern generation and fault simulation capabilities. Automatic Test Pattern Generation (ATPG) and fault simulation tools at structural and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented. These tools can be used separately, or in multiple applications, for test pattern generation of digital circuits. In order to link different tools together and with commercial design systems, respectively a set of translators was developed. The functionality of the integrated design and test system was verified by several benchmark circuits.

Multi-level fault simulation of digital systems on decision diagrams

A new method for hierarchical fault simulation based on multi-level decision diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows one to reduce time expenses in the comparison to traditional gate-level fault simulation approach.

HDL-s and FPGA-s in digital design education

To teach digital design efficiently, advantages of the technology should be taken into account. In this paper, an overview is given how hardware description languages (HDL) and field-programmable gate arrays (FPGA) are used at Tallinn University of Technology in digital design education in various related courses. The courses are taught for IT-students with different background - computer engineering, electronics, etc. Observations made and experiences learnt from running the courses over few years are described.

Web-Based Environment for Digital Electronics Test Tools

This paper describes a concept and implementation of the web-based environment for providing access over the Internet to existing stand-alone digital electronics test tools. On the user side only ordinary web browser is sufficient. The environment is built according to the client- server three-tier concept using HTML, Java applets/servlets and MySQL as database backend for user tracking and management tasks. In this paper we discuss integration of two software systems into web- based environment. The paper presents the workflows that can be executed over the Internet and gives the experimental results for estimating the efficiency of the hierarchical ATPG.

Improved VHDL Input for High-Level Synthesis Tool xTractor

In this paper, an improved version of VHDL compiler for an academic high-level synthesis tool xTractor is presented. A synthesizable subset of behavioral VHDL, accepted by the compiler, is described in brief. Improvements that allow descriptions at higher abstraction level are outlined. The compiler translates the behavioral VHDL subset into control oriented flow-chart like internul description IRSYD. The mapping of higher abstraction level VHDL constructs into IRSYD is described in more details. A short description of the synthesis tool is presented

Collaborative Distributed Computing in the Field of Digital Electronics Testing

Computation tasks used in digital design flow for test quality evaluation can require a lot of processor and memory resources. To speed up execution and to overcome memory restrictions, a collaborative computing approach was proposed in this paper. Web-based system architecture allows seamlessly aggregate many remote computers for one application. Efficient collaboration requires credit based priority concept, issues of task partitioning, task allocation, load balancing and model security must be handled. Experimental results show feasibility of proposed solution and gain in performance.

Collaborative Distributed Fault Simulation for Digital Electronic Circuits

In this paper we focus on the framework for aggregating adaptively computing resources in different enterprises for computation intensive applications. Concept and implementation of web-based collaborative system was presented to speed up fault simulation and to overcome the problem of memory limits in the case of very large digital circuits. Issues of task partitioning, task allocation, load balancing were handled, credit based priority concept was introduced. Experimental results show feasibility of the solution and gain in performance.

Web-Based Framework for Parallel Distributed Test

In this paper we describe Web-based distributed system suitable for acceleration of fault simulation in digital circuits. Framework has three-tier client server concept. Java applets are used for user interfaces. Java servlet on master server supports communication, task partitioning, user tracking, data management, etc. HTTP protocol based solution is used, since it is well established and flexible in firewall- protected environments. Reuse of existing test tools by encapsulation into Java agents extends the lifecycle and value of these tools. Considerable fault simulation speedup was gained in experiments. Two types of fault set partitioning were tried: adjacent fault selection and random fault selection. The latter is able to ensure more equal execution times for subtasks and therefore contributes to overall shorter parallel simulation time.

Distributed Approach for Genetic Test Generation in the Field of Digital Electronics

Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Digital test generation aims to find minimal set of test vectors to obtain maximum fault coverage for digital electronic circuits. In this paper we focus on distributed environment and parallelization of the computationally intensive genetic algorithm based test generation for sequential circuits. We discuss the concept and implementation of our system infrastructure, task partitioning, allocation, test generation algorithm and results.

Web-based framework for distributed remote laboratory in the field of digital system test

In this paper we describe web-based distributed framework for building software systems to facilitate high-quality teaching, learning and research of digital circuits design and test. Internet-based working becomes a necessity and a reality in modern society and the growing number of developed remote laboratories shows the perspectives of expanded use of the internet in learning process. On-line systems allow to use existing learning tools effectively by many users over the network organizing their experiments in a queue, storing the results for later downloading. The framework we describe has three-tier client server concept and supports massively parallel computing. There is one master server, several application servers and arbitrary number of users. Java applets are used as user interfaces. Coordinating Java servlet running on master server is responsible for communication support, task scheduling, task partitioning, user tracking, data management, etc. HTTP protocol based solution is used, since it is well established and flexible in firewall-protected environments. Reuse of existing CAD tools by encapsulation into Java agents extends the lifecycle and value of these tools.