Elmet Orasson

Fast test cost calculation for hybrid BIST in digital systems

The paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform a core test with minimum cost of both time and memory, and without losing test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.

Hybrid BIST Optimization Using Reseeding and Test Set Compaction

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.

Functional Built-In Self-Test for processor cores in SoC

A methodology for organization of at-speed functional Built-In Self-Test in processors, based on real functional routines is presented. The proposed self-test includes on-chip test application and response collection by using the functionality of the processor under test. We use divide-and-conquer approach. At component level, tests are targeting faults in components. At processor level, the functionality of the processor is used to apply functional test patterns to each component at-speed. Differently from usual Built-in Self-Test schemes, the test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system.

Hybrid BIST optimization using reseeding and test set compaction

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.

Optimization of the Store-and-Generate Based Built-in Self-Test

Classical built-in self-test (BIST) architectures are usually relying on linear feedback shift registers (LFSR) for test set generation and test response compaction. This paper is based on extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and reduce test time. We will propose a method, based on store-and-generate approach, to find the optimal balance between pseudorandom and stored deterministic test patterns. The objective is to minimize the test time at given memory constraints, without losing test quality. We propose an iterative search method and the experimental results on benchmark circuits have proved the efficiency of the proposed approach for hybrid BIST optimization

Scalable algorithm for structural fault collapsing in digital circuits

The paper presents a new algorithm for structural fault collapsing to reduce search space for test generation, speed up fault simulation and make fault diagnosis easier in digital circuits. The proposed method is based on hierarchical topology analysis of the circuit description. First, the gate-level circuit will be converted into a macro-level network of fan-out-free regions each of them represented by a BDD. This conversion procedure represents the first step of fault collapsing, resulting in a compressed BDD model for representing the remaining set of fault sites. The paper presents an algorithm which implements a complementary step for further fault collapsing, and is carried out at the macro level by topological reasoning of equivalence and dominance relations between the nodes of BDDs. The algorithm has linear complexity and is implemented as a scalable fault collapsing procedure. We introduce higher and lower bounds for structural fault collapsing and provide statistics of distribution of fault collapsing results for a broad set of benchmark circuits. Experimental research has demonstrated better results for structural fault collapsing compared with state-of-the-art.

Teaching advanced test issues in digital electronics

An environment targeted to e-learning is presented for teaching advanced test issues in digital electronics. Digital circuits and systems are getting more and more complex, and in the same time the requirements for the quality of systems are getting higher and higher. This is the reason why the importance of testing as an engineering task has started to grow extremely fast. An environment which consists of a set of Java applets has been created to help the students to improve their understanding of test. The tools support university courses on digital electronics, computer hardware, testing and design for testability to learn by hands-on exercises how to generate test patterns, and how to analyze their quality. The tasks chosen for hands-on training represent simultaneously real research problems, which allow to foster in students critical thinking, problem solving skills and creativity.

Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems

This paper describes an optimization technique for finding test solutions for embedded core-based systems. For embedded systems the traditional external tester based test is often unfeasible and therefore different self-test solutions are sought after. Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems. The results will be illustrated with several experimental results.