Efraim Aloni

C-Flash: An Ultra-Low Power Single Poly Logic NVM

An ultra-low power logic NVM has currents <10 nA/cell in all operating regimes, high programming/erase speeds, excellent endurance/retention and allows strong Vdd fluctuations. The memory uses CMOS inverter read-out principle (C-Flash) and F-N injection for programming and erase with voltages below +5 V. The memory is intended for RFID and advanced mobile applications requiring small/middle sized embedded memory modules.

Plasma-induced charging in two bit per cell SONOS memories

Plasma induced charging in oxide-nitride-oxide (ONO) stacks and its influence on device and reliability performance were investigated on microFlash/spl reg/ two bit per cell memory devices. Experimental data indicate that UV radiation combined with the voltage built-up at the electrodes is the main cause of the observed Vt increase. Charging effects are more pronounced for scaled down devices with narrow word lines. An enhanced narrow channel effect is shown to be related to negative charges trapped in the nitride of ONO at the edges of the memory cell. Charging leads to the degradation of retention properties and results in the increased Vt spread. To decrease ONO charging a complex of measures was implemented that included screening of problematic equipment, development of special protecting circuits and improvement of the device design.

Extending endurance of NROM memories to over 10 million program/erase cycles

We report on NROM (nitride read only) memory with enhanced endurance/retention. A novel “refresh” is introduced into the cycling algorithm to exclude parasitic electron trapping in the memory transistor. Negative gate pulses are applied when the drain voltage in the erase procedure reaches the threshold value. The memory stack is optimized to allow injection of holes from the substrate through the bottom oxide (BOX). More than 10 million program/erase (P/E) cycles with excellent retention are easily achieved.