Micha Gutman

Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

In this letter, we report on the suppression of the erased state threshold voltage drift (room temperature V/sub t/ drift) in cycled two-bit per cell silicon-oxide-nitride-oxide-silicon memory. Room temperature V/sub t/ drift is significantly decreased by using bottom oxide (BOX) with the thickness T/sub BOX/<50 /spl Aring/. Excellent retention properties are preserved for T/sub BOX/ up to 33 /spl Aring/. The results of single-cell studies were confirmed on 2 Mb memory arrays that underwent up to 1000 program/erase cycles. Peculiarities of hole injection into the nitride of oxide-nitride-oxide in the erase operation are considered for explanation of the observed results. The improvement is associated with a lesser amount of holes used in the erase.

Plasma-induced charging in two bit per cell SONOS memories

Plasma induced charging in oxide-nitride-oxide (ONO) stacks and its influence on device and reliability performance were investigated on microFlash/spl reg/ two bit per cell memory devices. Experimental data indicate that UV radiation combined with the voltage built-up at the electrodes is the main cause of the observed Vt increase. Charging effects are more pronounced for scaled down devices with narrow word lines. An enhanced narrow channel effect is shown to be related to negative charges trapped in the nitride of ONO at the edges of the memory cell. Charging leads to the degradation of retention properties and results in the increased Vt spread. To decrease ONO charging a complex of measures was implemented that included screening of problematic equipment, development of special protecting circuits and improvement of the device design.

Computer model of the trapping media in micro FLASH® memory cells

A computer model for the dielectric trapping layer in the microFLASH memory transistor is developed. Due to local trapping of injected charges in corresponding devices the problem of lateral charge migration in the plane parallel to the transistor channel becomes of principal importance. Molecular Dynamics method was used to design a cluster of atoms with dielectric properties and to perform computer simulation of the redistribution of the injected charges in the program/erase processes. The charge distributions obtained on the basis of proposed model are strongly influenced by Coulomb repulsion between the trapped charge carriers. This effect leads to non-Gaussian discrete space distribution of trapped charges and significantly influences the endurance of the memory device. We demonstrate that large densities of traps and injected carriers are strongly correlated, limiting the amount of charge that can be accumulated in the programming process. The model allows select optimum parameters of the trapping layer to ensure high retention properties of the memory cells.

ONO charging at different stages of microFlash/sup /spl reg// process flow

In-process ultraviolet (UV) stimulated charging of ONO (oxide-nitride-oxide) stack is observed in fieldless microFlash (NROM) memory arrays. This problem is solved by introducing a UV blocking layer into the D1 dielectric. In this paper we discuss an alternative approach to the solution of charging problem. A micropartitioning technique is described that allows to screen out the operations responsible for ONO charging and corresponding equipment.