Alessandro Italia

A 1-mW 1.13–1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors

A low-power wideband LC VCO has been designed and implemented in a 90-nm CMOS technology. Wide tuning range, low phase noise and low power consumption are achieved thanks to the adopted LC tank, which makes use of shunt-connected switched-coupled inductors and a proper arrangement of varactors. The shunt-connected switched-coupled inductors provide coarse tuning and phase noise optimization without using amplitude calibration loop or trimming of the bias current. The proposed varactors configuration employs accumulation mode thin and thick MOS devices, which has been differently biased to obtain tuning range maximization along with minimization of the amplitude-to-phase noise conversion. The LC-tank topology and inductor layout have been properly designed to attain a die area comparable to a single-inductor VCO, taking advantage of the inductors mutual coupling. The VCO exhibits a phase noise at 1-MHz offset frequency lower than -114 dBc/Hz over the entire tuning range and achieves -126.1 dBc/Hz at 1.2 GHz. It provides a tuning range of 51% from 1.13 GHz to 1.9 GHz with a tuning voltage ranging from 0 to 1.2 V. Despite a very low current consumption, which is 0.88 mA from a 1.2-V supply, the proposed VCO has the outstanding PFTN figure-of-merit of 10. The VCO core die area is 0.5 mm2.

A 3–5-GHz UWB Front-End for Low-Data Rate WPANs in 90-nm CMOS

A 3-5-GHz ultra-wideband front-end for low-data rate wireless personal area networks is presented in this paper. The circuit, fabricated in a 90-nm CMOS technology, includes a Gaussian-envelope carrier-based transmitter, a direct-conversion down-converter, and an LO frequency synthesizer. A highly accurate Gaussian pulse shape is achieved by using a nonlinear pulse-forming approach, which provides a spectral efficiency of 38%. Moreover, a side-lobe rejection higher than 27 dB is reached without external filters. The transmitter achieves a peak pulse repetition frequency of 500 MHz supporting both pulse-position modulation and binary phase-shift-keying modulation schemes. It includes a baseband digital modulator, which implements spreading and time-hopping functions, and can be easily programmed to support different data rates, mean pulse repetition frequencies, and modulation timing parameters. The down-converter exploits a single-ended low-noise amplifier to avoid the off-chip wideband balun and minimize power consumption. It provides a 29-dB conversion gain and 5.2-dB noise figure while drawing only 8 mA. Operating from a 1.2-V supply, the overall front-end dissipates 42 pJ/pulse in RX mode and 56 pJ/pulse in TX mode.

A 1.2-mW CMOS frequency synthesizer with fully-integrated LC VCO for 400-MHz medical implantable transceivers

An ultra low-power frequency synthesizer for 400-MHz medical implantable transceivers was designed and fabricated in a 0.13-µm CMOS technology. The circuit is implemented by means of an integer-N phase-locked loop, which features a fully-integrated LC VCO and 160/480-kHz programmable channel steps. The frequency synthesizer exhibits a phase noise better than −96 dBc/Hz at 100-kHz offset frequency for all the supported channels. The measured settling time is around 500 µS and the reference spurs are lower than −52 dBc. The power consumption of the frequency synthesizer is only 1.2 mW from a 1.2-V supply.

A 0.13-

This paper presents a Colpitts-based voltage-controlled oscillator (VCO) for W-band radar applications. In the proposed circuit, the oscillation signal is directly drawn from the switching transistor bases by means of the primary winding of a transformer tank, while the secondary winding drives the output buffer. This solution improves both tuning range and oscillation swing with respect to traditional millimeter-wave VCO topologies without increasing power supply. The oscillator is implemented in a 0.13-μm SiGe BiCMOS technology, along with high-frequency dividers to enable low-frequency testing. The VCO exhibits a phase noise of -99.3 dBc/Hz at 1-MHz offset from an oscillation frequency of 76 GHz and a tuning range of 4.9% with a consumption of 65 mW at 2.5-V power supply. The VCO is also used to drive a two-stage power amplifier in a fully integrated W-band transmitter that is able to deliver an overall output power as high as 15 dBm at 76 GHz.

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In this paper a novel figure of merit for the rating of integrated transformers is presented. The proposed parameter provides a more reliable performance characterization compared to previously reported ones (i.e., insertion loss and maximum available gain), since it is inherently related to the maximization of the available output power in tuned-load RF circuits. The new figure of merit is used to evaluate the effect of different substrate management approaches on the performance of silicon integrated transformers.

SiGe BiCMOS Colpitts-Based VCO for

In this paper, a design methodology for the optimization of transformer-loaded RF circuits is presented. The optimization procedure is based on a novel figure of merit for the integrated transformer (namely the transformer characteristic resistance), which was introduced to quantify its performance when operated as a tuned load. Using the proposed approach, a highly linear up-converter for 5-GHz wireless LAN applications was implemented in a 45-GHz-f/sub T/ SiGe HBT technology. The circuit achieved an output 1-dB compression point of 4.5 dBm and a power gain of 18 dB, while drawing only 34 mA from a 3-V power supply.

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In this paper, an ultra low-power wideband frequency synthesizer is demonstrated in a 90-nm CMOS technology. The circuit is intended for low data-rate sub-GHz transceivers and is based on a programmable integer-TV phase-locked loop. The frequency synthesizer in cooperation with divide-by-two frequency dividers is able to provide quadrature LO signals in the 300–470 MHz and 750–950 MHz RF bands with a 150-kHz frequency step. It provides a phase noise better than −91 dBc/Hz at 150-kHz offset frequency for all the supported channels. The measured settling time is around 350 μS and the reference spurs are lower than −48 dBc. The power consumption of the frequency synthesizer is only 1.7 mW from a 1.2-V supply.

-Band Radar Transmitters

This paper presents a high-linearity monolithic up-converter for 5-GHz wireless LAN applications. The circuit, implemented in a 40-GHz-f/sub T/ SiGe HBT technology, includes a variable-gain amplifier (VGA) and a double balanced mixer. By using an integrated balun at the RF output, the up-converter guarantees an output 1-dB compression point (OCP1) of 4 dBm, while drawing a quiescent current as low as 34 mA from a 3-V power supply. A power gain of 11 dB is also achieved. Moreover, a digital control is included, providing a linear-in-dB gain characteristic with a 45-dB power gain range.

The transformer characteristic resistance and its application to the performance analysis of silicon integrated transformers

A 400-MHz ultra low-power radio front-end for medical implantable applications has been implemented in a 0.13-µm CMOS technology. The circuit consists of an up-converter, a down-converter, and a LO frequency synthesizer. The up-converter employs a push-pull PA, which achieves a saturated output power of 0 dBm with a maximum power added efficiency of 32%. Moreover, the up-converter exhibits a −30-dBc ACPR at an output power of −0.5 dBm with a 200 kbit/s GFSK input signal. The down-converter provides excellent linearity performance exhibiting an output compression point of 1.13 Vpp, an IIP3 of −23 dBm, and an IIP2 of 8.7 dBm despite a current consumption as low as 1.5 mA. It has a 45-dB conversion gain and a 7.4-dB noise figure. The LO frequency synthesizer features a fully-integrated LC VCO and programmable channel steps. It provides a phase noise better than −96 dBc/Hz at 100-kHz offset and a spur rejection of −52 dBc. Operating from a 1.2-V supply, the overall front-end draws 3 mA in receive mode and 4.5 mA in transmit mode.

Design methodology for the optimization of transformer-loaded RF circuits

An image-reject down-converter for IEEE 802.11a and ETSI HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-fT silicon bipolar process. The circuit integrates a variable-gain low noise amplifier and a double-balanced mixer along with passive image rejection filters. It exhibits a 4-dB noise figure and a power gain of 23 dB. By reducing the low noise amplifier gain by 9 dB (thanks to a 1-bit gain control), the down-converter achieves an input 1-dB compression point of –14 dBm, while drawing only 23 mA from a 3-V supply voltage. The adopted filtering approach provides an image rejection ratio higher than 60 dB.