Giuseppina Sapone

A 3–10-GHz Low-Power CMOS Low-Noise Amplifier for Ultra-Wideband Communication

A 90-nm CMOS low-noise amplifier (LNA) for 3-10-GHz ultra-wideband (UWB) applications is presented. The circuit adopts a single-ended dual-stage solution. The first stage is based on a current-reuse topology and performs UWB (3-10 GHz) input matching. The second stage is a cascode amplifier with resonant load to enhance gain and reverse isolation. Thanks to both the circuit solution and design approach, the LNA provides input matching, low noise, flat gain, and small group-delay variation in the UWB frequency range at minimum power consumption. The design is also conceived to cope with application issues such as low-cost off-chip interfaces and electrostatic discharge robustness. Measurements exhibit a 12.5-dB power gain in a 7.6-GHz 3-dB bandwidth, a minimum noise figure of 3 dB, a reverse isolation better than 45 dB up to 10.6 GHz, and a record small group-delay variation of ±12 ps. The LNA draws 6 mA from a 1.2-V power supply.

A 3–5-GHz UWB Front-End for Low-Data Rate WPANs in 90-nm CMOS

A 3-5-GHz ultra-wideband front-end for low-data rate wireless personal area networks is presented in this paper. The circuit, fabricated in a 90-nm CMOS technology, includes a Gaussian-envelope carrier-based transmitter, a direct-conversion down-converter, and an LO frequency synthesizer. A highly accurate Gaussian pulse shape is achieved by using a nonlinear pulse-forming approach, which provides a spectral efficiency of 38%. Moreover, a side-lobe rejection higher than 27 dB is reached without external filters. The transmitter achieves a peak pulse repetition frequency of 500 MHz supporting both pulse-position modulation and binary phase-shift-keying modulation schemes. It includes a baseband digital modulator, which implements spreading and time-hopping functions, and can be easily programmed to support different data rates, mean pulse repetition frequencies, and modulation timing parameters. The down-converter exploits a single-ended low-noise amplifier to avoid the off-chip wideband balun and minimize power consumption. It provides a 29-dB conversion gain and 5.2-dB noise figure while drawing only 8 mA. Operating from a 1.2-V supply, the overall front-end dissipates 42 pJ/pulse in RX mode and 56 pJ/pulse in TX mode.

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This paper presents a Colpitts-based voltage-controlled oscillator (VCO) for W-band radar applications. In the proposed circuit, the oscillation signal is directly drawn from the switching transistor bases by means of the primary winding of a transformer tank, while the secondary winding drives the output buffer. This solution improves both tuning range and oscillation swing with respect to traditional millimeter-wave VCO topologies without increasing power supply. The oscillator is implemented in a 0.13-μm SiGe BiCMOS technology, along with high-frequency dividers to enable low-frequency testing. The VCO exhibits a phase noise of -99.3 dBc/Hz at 1-MHz offset from an oscillation frequency of 76 GHz and a tuning range of 4.9% with a consumption of 65 mW at 2.5-V power supply. The VCO is also used to drive a two-stage power amplifier in a fully integrated W-band transmitter that is able to deliver an overall output power as high as 15 dBm at 76 GHz.

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This paper presents the design and the measurement results of a 3-5-GHz down-converter fabricated in a 90-nm CMOS technology. The circuit consists of a single-ended resistive-feedback low-noise amplifier and two I/Q double-balanced mixers. A transformer-based on-chip single-ended-to-differential conversion allows gain and noise performance to be optimized at a very-low power. A post-layout stability analysis on the LNA is also reported, giving the guidelines to avoid possible oscillations introduced by the single-ended LNA. The down-converter achieves a 23-dB conversion gain, a noise figure of 3.4 dB, and an input third-order intercept point of -8 dBm, while drawing only 9 mA from a 1.2-V supply voltage.

SiGe BiCMOS Colpitts-Based VCO for

A wideband low-noise amplifier for 3-5-GHz UWB applications is presented. The circuit was fabricated in a 90-nm CMOS process. It consists of a complementary PMOS / NMOS pair, which provides wideband input matching, while the second stage adopts a transformer-loaded cascode topology. The amplifier achieves a power gain of 13.5 dB and a 3.1-to-5.9-GHz 3-dB gain bandwidth, while it features a noise figure of 2.8 dB. Wideband S-parameter measurements reveal excellent input matching and high reverse isolation in the whole UWB frequency range, i.e. 3.1 to 10.6 GHz. The circuit draws only 4.5 mA from a 1.2-V supply voltage.

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This paper presents a 3-5 GHz ultra-wideband radio front-end for low data-rate wireless personal area network applications. The circuit, implemented in a 90-nm CMOS technology, includes a carried-based ultra-wideband transmitter, a sub-optimal coherent down-converter and a low-power LO signal generator. Thanks to a pseudo-Gaussian pulse generator, the transmitter is able to run up to 500 Mpps satisfying the FCC mask requirements with no filter and high spectral efficiency. The down-converter exploits a single-ended low-noise amplifier to minimize power consumption. It also performs on-chip single-ended-to-differential conversion of the RF signal by using an integrated transformer. The down-converter exhibits a 23-dB conversion gain and a double-sideband noise figure of 3.4 dB. The LO signal is generated by a low-power wideband LC VCO, which draws only 1.5 mA. The current consumption of the radio front-end is 15 mA in receive mode and 24 mA in transmit mode.

-Band Radar Transmitters

A transceiver front-end for 5 GHz wireless local area network applications has been designed and implemented in a low-cost 46 GHz fT pure-silicon bipolar technology. The transceiver front-end adopts a superheterodyne sliding-IF architecture and consists of a down-converter, an up-converter and an LO frequency synthesiser. By exploiting a 1 bit variable-gain low-noise amplifier, the down-converter is able to provide an excellent noise figure of 4 dB while ensuring an input 1 dB compression point of −10 dBm with a current consumption of 25 mA from a 3 V supply voltage. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1 dB compression point of 5.3 dBm although consuming only 45 mA from a 3 V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35 dB dynamic range. The LO frequency synthesiser is implemented by means of an integer-N phase-locked loop. It features a phase noise of −117 dBc/Hz at 1 MHz offset from the centre frequency of 4.1 GHz and exhibits a tuning range of 1.2 GHz, from 3.47 to 4.65 GHz. The LO frequency synthesiser draws 20 mA from a 3 V supply voltage.

A Low-Power 3-5-GHz UWB Down-Converter with Resistive-Feedback LNA in a 90-nm CMOS Process

Circuit design techniques for integrating low-power multi-standard WLAN transceivers are presented in this paper. Several circuital approaches have been implemented and successfully demonstrated for the most critical blocks of a WLAN transceiver. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1-dB compression point of 5.3 dBm, while consuming only 45 mA from a 3-V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35-dB dynamic range. In the receiver chain, a variable-gain LNA allows excellent noise figure and linearity performance to be achieved with low power consumption. The PLL makes use of a transformer-based VCO featuring low-phase noise and wide tuning range performance.

A 90-nm CMOS two-stage low-noise amplifier for 3-5-GHz ultra-wideband radio

In this paper the measured performance of a 3-5 GHz low-power up-converter is presented. The circuit is based on a current-reuse topology with resistive load. It was implemented in a standard low-cost 0.25-μm CMOS technology. The up-converter achieves 3.8-dB of power gain, an output 1-dB compression point of -10.8 dBm, and a 8-dB single-sideband noise figure, while drawing only 2.3 mA from a 1.5-V supply voltage. An operating bandwidth of 1.5 GHz was measured. The reported comparison carried out with the state-of-the-art of wideband/low-power mixers demonstrates that excellent RF performance has been achieved. The proposed circuit is in accordance with the wideband/low-power requirements of 3-5 GHz ultra-wideband WPANs.