Elizabeth A. Kolawa

Films of Ni–7 at% V, Pd, Pt and Ta–Si–N as diffusion barriers for copper on Bi2Te3

Films of Ni–7 at% V, Pt, Pd, and Ta40Si14N46, each approximately 100 nm thick, were magnetron-deposited and interposed between about 250 nm thick copper overlayers and Bi2Te3 single-crystalline substrates. The samples were then annealed in vacuum up to 350 degrees C. The performance of the metal and the tantalum-silicon-nitride films as diffusion barriers for in-diffusion of Cu and out-diffusion of Bi and Te was evaluated by 2.0 MeV 4He backscattering spectrometry and x-ray diffraction. The Ni–7 at% V, Pd and Pt films all fail to prevent interdiffusion of Cu and Bi2Te3 after a few hours of annealing at 200 degrees C. However, the Ta40Si14N46 barrier preserves the integrity of the contact after 250 degrees C for 50 h and 350 degrees C for 1 h anneals. These results confirm the superior characteristics of the metal-silicon-nitride films as diffusion barriers.

Development of Thick-Film Thermoelectric Microcoolers Using Electrochemical Deposition

Advanced thermoelectric microdevices integrated into thermal management packages and low power, electrical source systems are of interest for a variety of space and terrestrial applications. By shrinking the size of the thermoelements, or legs, of these devices, it becomes possible to handle much higher heat fluxes, as well as operate at much lower currents and higher voltages that are more compatible with electronic components. The miniaturization of state-of-the-art thermoelectric module technology based on Bi 2 Te 3 alloys is limited due to mechanical and manufacturing constraints for both leg dimensions (100–200 μm thick minimum) and the number of legs (100–200 legs maximum). We are investigating the development of novel microdevices combining high thermal conductivity substrate materials such as diamond, thin film metallization and patterning technology, and electrochemical deposition of thick thermoelectric films. It is anticipated that thermoelectric microcoolers with thousands of thermocouples and capable of pumping more than 200 W/cm 2 over a 30 to 60 K temperature diffrence can be fabricated. In this paper, we report on our progress in developing an electrochemical deposition process for obtaining 10–50 μm thick films of Bi 2 Te 3 and its solid solutions. Results presented here indicate that good quality n-type Bi 2 Te 3 , n-type Bi 2 Te 2.95 Se 0.05 and p-type Bi 0.5 Sb 1.5 Te 3 thick films can be deposited by this technique. Some details about the fabrication of the miniature thermoelements are also described.

Development of robust analog and mixed-signal electronics for extreme environment applications

The Integrated Circuits and Systems Laboratory at the University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. In this paper, we present system level and transistor level extreme environment design techniques and measurement results from several test circuits. The design techniques focus on developing high performance operational transconductance amplifiers (OTAs) and op-amps that can operate over a wide temperature range. The test circuits include a 3.3-V ping-pong op-amp, a 3.3-V rail-to-rail I/O op-amp capable of driving resistive loads, and a temperature stable voltage reference and current reference.

Multi-bias dependence of threshold voltage, subthreshold swing, and mobility in G/sup 4/-FETs

Systematic measurements of four-gate SOI transistors (G/sup 4/-FET) are presented. Methods of extraction of the threshold voltage, subthreshold swing, and mobility in the linear region are discussed and results are shown. The extracted parameters demonstrate the complex dependence of the multi-gate biases, which is explained. A new extraction technique for the carrier mobility and effective width of devices with isolated multiple gates is proposed.

Design for ASIC reliability for low-temperature applications

A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges

Die Attachment for −120°C to +20°C Thermal Cycling of Microelectronics for Future Mars Rovers—An Overview

Jet Propulsion LaboratoryCalifornia Institute of TechnologyPasadena, California 91109•Also: Consulting Physicist. Mountain View, CaliforniaABSTRACTActive thermal control for electronics on Mars Roversimposes a seriotm penalty in weight, volume, power consumption,and reliability. Thus, we propose .that thermal control beeliminated for future Rovers. From a functional standpoint there isno reason that the electronics could not operate over the entiretemperature range of the Martian environment, which can varyfrom a low of =-90°C to a high of = +20°C during the Martiannight and day. The upper end of this range is well within that forconventional electronics. Although the lower end is considerablybelow that for which conventional---even high-reliability--electronics is designed or tested, it is weg established thatelectronic devices can operate to such low temperatures. Theprimary concern is reliability of the overall electronic system,especially in regard to the numerous daily temperature cycles thatit would experience over the duration of a mission on Mars.Accordingly, key reliability issues have been identified forelimination of thermal control on future Mars Rovers. One ofthese is attachment of semiconductor die onto substrates and intopackages. Die attachment is critical since it forms a mechanical,thermal and electrical interface between the electronic device andthe substrate or package. This paper summarizes our initial inves-tigation of existing information related to this issue, in order toform an opinion whether die attachment techniques exist, or couldbe developed with reasonable effort, to withstand the Mars thermalenvironment for a mission duration of approximately I year.Our conclusion, from a review of fiterature and personal con-tacts, is that die attachment can be made sufficiently reliable tosatisfy the requirements of future Mars Rovers. Moreover, it ap-pears that there are several possible techniques from which tochoose and that the requirements could be met by judicious selec-tion from existing methods using hard solders, soft solders, ororganic adhesives.Thus. from the standpoint of die attachment, it appears feasi-ble to eliminate thermal control for Rover electronics. We recom-mend that this be further investigated and verified for the specifichardware and thermal conditions appropriate to Mars Rovers.

Developments in Radiation-Hardened Electronics Applicable to the Vision for Space Exploration

The Radiation Hardened Electronics for Space Exploration (RHESE) project develops the advanced technologies required to produce radiation hardened electronics, processors, and devices in support of the anticipated requirements of NASAs Constellation program. Methods of protecting and hardening electronics against the encountered space environment are discussed. Critical stages of a spaceflight mission that are vulnerable to radiation-induced interruptions or failures are identified. Solutions to mitigating the risk of radiation events are proposed through the infusion of RHESE technology products and deliverables into the Constellation programs spacecraft designs.

Approach to Extrapolating Reliability of Circuits Operating in a Varying and Low Temperature Range

We present an approach to extrapolating circuit reliability to use conditions with a varying and low temperature range. The approach integrates the impact of the statistical nature of transistor lifetime on circuit reliability to give a more realistic circuit reliability projection. Even though the approach is demonstrated for low temperature applications by focusing on hot carrier aging failure mechanism, it can be applied and easily extended to other failure mechanisms for any varying temperature operating conditions

Development of robust analog electronics at the University of Tennessee for NASA/JPL extreme environment applications

The INSYTE (Integrated Circuits and Systems) Laboratory at The University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. This work is being targeted for Mars surface applications where the temperature can vary from -1200/spl square/C to +20/spl square/C depending on time of day and location. In this paper we present both robust analog design techniques and measurement results from several test circuits. The design techniques focus on developing high performance OTAs and op-amps that can operate over a wide temperature range. The test circuits include a 3.3 V ping-pong op-amp and a 3.3 V rail-to-rail I/O op-amp capable of driving resistive loads.

Design challenges and methodology for developing new integrated circuits for the robotics exploration of the solar system

Next generation space-based robotics systems will be constructed using distributed architectures where electronics capable of working in the extreme environments of the planets of the solar system are integrated with the sensors and actuators in plug-and-play modules and are connected through common multiple redundant data and power buses. Challenges for development of integrated circuits for these robotic systems deal with the reliable operation of these systems under extreme planetary environments. These challenges are compounded by a complementary set of packaging and assembly issues that address the reliability of the system from the mechanical point of view. Without exception integrated electronics developed for space systems will have to use existing commercial device and VLSI manufacturing technologies. Because of the severe difference between the extreme environment of the solar system planets and Earth, IC designers of space systems have to examine the performance of all the devices in the extreme environment conditions and define a new set of design rules and models that predicts the performance and life cycle of these technologies.