M.M. Mojarradi

Investigation of the four-gate action in G/sup 4/-FETs

The four-gate silicon-on-insulator transistor (G/sup 4/-FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G/sup 4/-FET are analyzed, based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications.

Low-frequency noise in SOI four-gate transistors

Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G/sup 4/-field-effect transistor] are reported. The noise power spectral density as a function of biasing conditions is presented and compared for surface and volume conduction modes. It is shown that, for the same drain current, the volume of the transistor generates less noise than its surface. The possible transition from carrier-number fluctuations to mobility fluctuations as the conducting channel is moved away from the surface toward the volume is also discussed.

Back-gate and series resistance effects in LDMOSFETs on SOI

Detailed experimental results are used to develop a new model for the linear region of operation of lateral DMOSFETs (LDMOSFETs) on silicon-on-insulator (SOI) that includes the influence of the buried oxide and back-gate. Back-gate biasing results in double-channel conduction and bias-dependent series resistance. Pertinent techniques for parameter extraction are presented and contrasted to those currently used in low-voltage SOI MOSFETs. The typical feature of LDMOSFETs is the significant change in series resistance as the back-gate is driven from accumulation to inversion. The model allows a clear identification of the architectural and technological parameters of the device.

Development of robust analog and mixed-signal electronics for extreme environment applications

The Integrated Circuits and Systems Laboratory at the University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. In this paper, we present system level and transistor level extreme environment design techniques and measurement results from several test circuits. The design techniques focus on developing high performance operational transconductance amplifiers (OTAs) and op-amps that can operate over a wide temperature range. The test circuits include a 3.3-V ping-pong op-amp, a 3.3-V rail-to-rail I/O op-amp capable of driving resistive loads, and a temperature stable voltage reference and current reference.

Four-Gate Transistor Voltage-Controlled Negative Differential Resistance Device and Related Circuit Applications

A novel voltage-controlled negative differential resistance device, using complementary SOI four-gate transistors (G4-FETs) is presented. Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstrated

Temperature-compensated reference circuits for SOI

Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G/sup 4/-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-/spl mu/m partially depleted (PD)-SOI process.

Operating SOI CMOS technology in extreme environments

Partially-depleted SOI CMOS devices fabricated in a 0.35 /spl mu/m technology on UNIBOND material were evaluated for electronics applications requiring robust operation under extreme environment conditions consisting of: low and/or high temperatures, and under substantial radiation exposure. The threshold voltage and effective mobility were determined across temperature for SOI CMOS. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 /spl mu/m partially-depleted SOI CMOS technology Is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

Design challenges and methodology for developing new integrated circuits for the robotics exploration of the solar system

Next generation space-based robotics systems will be constructed using distributed architectures where electronics capable of working in the extreme environments of the planets of the solar system are integrated with the sensors and actuators in plug-and-play modules and are connected through common multiple redundant data and power buses. Challenges for development of integrated circuits for these robotic systems deal with the reliable operation of these systems under extreme planetary environments. These challenges are compounded by a complementary set of packaging and assembly issues that address the reliability of the system from the mechanical point of view. Without exception integrated electronics developed for space systems will have to use existing commercial device and VLSI manufacturing technologies. Because of the severe difference between the extreme environment of the solar system planets and Earth, IC designers of space systems have to examine the performance of all the devices in the extreme environment conditions and define a new set of design rules and models that predicts the performance and life cycle of these technologies.

Application of commercial electronics in the motors and actuator systems for Mars surface missions

Commercial-off-the-shelf electronic components (COTS) offer a very low cost and attractive solution for construction of electronic systems for Mars missions, including the actuator electronic systems for the Mars Rovers. One issue with using COTS lies in the difference between their specified operating temperature range (-55/spl deg/C to125/spl deg/C for military components) and the temperatures observed at the surface of Mars (-120/spl deg/C to 20/spl deg/C). To compensate for the difference between these temperatures, most of the electronics are placed in a central warm-electronics-box or WEB. In some cases, such as the distributed control system for the actuators, the electronic assemblies that are to be placed on or near the motors are outside of the central WEB. The experimental search consists of two steps. First, a short functional/non-functional test at -120/spl deg/C is used to identify and narrow down the number of candidate COTS that can work at very cold temperatures. More extensive characterization of the parts that passes the short test is performed to determine the operating margins and estimate the thermal cycle life capability for the COTS parts. Finally, the operating margins of the COTS parts are published as a set of specifications.

Reliability assessment of high temperature electronics and packaging technologies for Venus mission

In this paper, the potentials of the current state-of-the-art electronics and packaging technologies for Venus missions is evaluated and intend to address the survivability and reliability of the selected technologies and develop design-for-reliability guidelines for mission integration.