Elkim Roa

A Current-Efficient, Low-Dropout Regulator with Improved Load Regulation

This paper presents a novel topology for LDO regulators, improving load regulation with very low quiescent current. The core of the circuit is made by operating the pass transistor in the linear region, achieving an area reduction above 90%, reducing the gate capacitance and therefore improving loop response. The proposed structure to improve the load regulation is based on transconductance cells and current mirrors, allowing to sink the remaining energy on the compensation capacitor without affecting battery lifetime. This design was developed in AMS 0.35 mum technology and occupies only 0.025 mm 2 with a quiescent current of 10 muA. The proposed LDO can deliver 50 mA @ 3.3 V with 200 mV dropout, a load regulation of 591 nV/mA and is able to recover within 3 mus for any load transient. Extensive post-layout simulations and monte carlo analysis were performed in order to validate these results.

A 2.7ua sub1-v voltage reference

A simplified voltage reference topology with low power consumption based on MOS transistors in weak inversion operation is presented. A 176 <i>mV</i> @ 27°<i>C</i> output voltage with a quiescent current of 2.7 μ<i>A</i> @ 3.3 <i>V</i> and a thermal coefficient of 8.8 μ<i>V/°C</i> in the temperature range of [-25; 100] °<i>C</i> had been achieved in measurement results. The circuit had been fabricated in AMS 0.35 μm C35B4 CMOS technology with an active area of 105 & <μμm x 212 μm.

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

This paper presents a small area CMOS current-steering segmented digital-to-analog converter (DAC) design used in a RF transmitter stage for 2.45GHz Bluetooth applications. The current source design strategy is based on an iterative scheme which variables are adjusted by a simple way, satisfying the requirements, minimizing power consumption and reaching the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy of small area consumption for the current-steering DAC design is included. The DAC was designed and implemented in 0.35mm 4M2P CMOS technolyogy. Some performance results obtained through experimental test are: chip active area of only 200mm-200mm, full scale output current of 700mA at 3.3V power supply, INL=0.3LSB, DNL=0.37LSB, SFDR=58dB for output sine wave frequency of Fout = 1MHz and Fs = 50MHz sampling frequency, SFDR=52dB for Fout = 1MHz and Fs = 10MHz.

On nonlinearity and noise trade-off in a low power 2.45 GHz CMOS LNA-mixer design

A detailed nonlinearity and noise analysis for a low noise amplifier and mixer design for 2.45 GHz Bluetooth applications is presented. As a result, the trade-off between noise, linearity, power consumption and impedance matching was considered as a design guide. A 2.45 GHz LNA-mixer has been designed and simulated in a 0.35 mum 4M2P CMOS technology to demonstrate the trade-off. Some performance results obtained through simulations are: N F=7.9 dB, voltage gain=27 dB, PII P3 = -14.4 dBm, IF = 1 MHz and power consumption of 15.6 mW at 3.3 V power supply.

A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC

In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.

A low-voltage bandgap reference source based on the current-mode technique

A low-voltage bandgap reference source design in CMOS AMS 0.35μ<i>m</i> is presented. For establishing a voltage reference of less than 1V, the current-mode technique is used. The current consumption of the proposed design is 84μ<i>A</i>; the supply voltage is 1.2V, and presents a small die area of 0.015<i>mm</i>². The average measurement results are: temperature coefficient of 114ppm/°C between [-25°C to 100°C], output voltage of 718mV and line regulation of 1.7mV/V.

A Digital Offset Reduction Method for Dynamic Comparators Based on Phase Measurement

This paper presents a low-cost technique to reduce offset voltage of a dynamic comparator. The proposed method is based on output-data phase measuring. A full-digital implementation is used to measure phase without impacting offset accuracy. Simulation and measured results show that the eye-diagram at the compartor input can be shifted up to 245mV due to offset, achieving a successful correction, and making the technique suitable for high-speed applications. The technique requires less than 500ns to achieve convergence and calibration. In this way, there is not need to break the communication link associated to the comparator. The circuit has been implemented in a 130nm TSMC standard CMOS process and detailed experimental results are shown along this document.

A merged RF CMOS LNA-Mixer design using geometric programming

This paper presents the design using geometric programming of a merged CMOS LNA-Mixer cell, intended for bluetooth application at 2.45GHz. A rigorous noise formulation taking into account on chip inductors non-idealities and parameters from inductor measurement results is provided. Design considerations to achieve geometric programming suitable expressions for noise, gain, and input matching, among others, are presented. As a result, the designed LNA-Mixer cell exhibits a single side band noise figure of 9.64dB, with a voltage gain of 21.5dB, input reflection co-efficient S11 of -28.7dB, in addition to a PIIP3=-2.06dBm. The circuit area is 0.93mm2 and consumes 8.67mW at 3.3V power supply in a 0.35μm CMOS process.

Mitigating Row Hammer attacks based on dummy cells in DRAM

This paper presents an alternative to prevent data corruption in DRAM memories due to Row Hammer attacks. The proposal is based on the usage of dummy cells connected to each row as attacks indicator. These special cells are characterized for having a higher sensitivity to coupling noise. The strategy was validated by simulations on a 65nm CMOS 64×64 memory array, including process variations for coupling and interconnections. Results keep congruence with a memory dedicated, state-of-art, process of 28nm. The main characteristics of this suggested solution are its low-complexity and low-hardware overhead.

A digital offset correction method for high speed analog front-ends

This paper presents an offset voltage correction technique for high-speed digital interfaces. Contrary to conventional way of measuring offset, the proposed technique is based on the phase measurement of a slicer output avoiding the input connection to a common mode voltage. A fully-digital implementation allows phase measurement maintaining offset accuracy. Proper operation of calibration technique is achieved when the input signal is comparable to the offset and sensitivity of the whole interface. Thus, the proposed method could be used during on-line operation, without breaking the communication link. The circuit has been implemented in a 130nm TSMC standard CMOS process, and simulation results show an offset reduction nearly 90% in the analog front-end with a low area overhead.