Hugo Daniel Hernández

A Current-Efficient, Low-Dropout Regulator with Improved Load Regulation

This paper presents a novel topology for LDO regulators, improving load regulation with very low quiescent current. The core of the circuit is made by operating the pass transistor in the linear region, achieving an area reduction above 90%, reducing the gate capacitance and therefore improving loop response. The proposed structure to improve the load regulation is based on transconductance cells and current mirrors, allowing to sink the remaining energy on the compensation capacitor without affecting battery lifetime. This design was developed in AMS 0.35 mum technology and occupies only 0.025 mm 2 with a quiescent current of 10 muA. The proposed LDO can deliver 50 mA @ 3.3 V with 200 mV dropout, a load regulation of 591 nV/mA and is able to recover within 3 mus for any load transient. Extensive post-layout simulations and monte carlo analysis were performed in order to validate these results.

A 2.7ua sub1-v voltage reference

A simplified voltage reference topology with low power consumption based on MOS transistors in weak inversion operation is presented. A 176 <i>mV</i> @ 27°<i>C</i> output voltage with a quiescent current of 2.7 μ<i>A</i> @ 3.3 <i>V</i> and a thermal coefficient of 8.8 μ<i>V/°C</i> in the temperature range of [-25; 100] °<i>C</i> had been achieved in measurement results. The circuit had been fabricated in AMS 0.35 μm C35B4 CMOS technology with an active area of 105 & <μμm x 212 μm.

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

This paper presents a small area CMOS current-steering segmented digital-to-analog converter (DAC) design used in a RF transmitter stage for 2.45GHz Bluetooth applications. The current source design strategy is based on an iterative scheme which variables are adjusted by a simple way, satisfying the requirements, minimizing power consumption and reaching the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy of small area consumption for the current-steering DAC design is included. The DAC was designed and implemented in 0.35mm 4M2P CMOS technolyogy. Some performance results obtained through experimental test are: chip active area of only 200mm-200mm, full scale output current of 700mA at 3.3V power supply, INL=0.3LSB, DNL=0.37LSB, SFDR=58dB for output sine wave frequency of Fout = 1MHz and Fs = 50MHz sampling frequency, SFDR=52dB for Fout = 1MHz and Fs = 10MHz.

A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC

In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.

Configurable low noise readout front-end for gaseous detectors in 130nm CMOS technology

A noise improved Charge Sensitive Amplifier (CSA) topology for a gaseous detector readout front-ends is presented. The proposed topology is based on the traditional cascode topology with addition of a PMOS to partially cancel the channel thermal noise and the flicker noise of the CSA input transistor. A noise improvement of about 23% was obtained without increasing power consumption. Additionally, the proposed circuit reduces the dependence of the noise on the detector capacitance. A chip with 5 front-ends channel implemented with the proposed CSA topology and a Semi-Gaussian shaper of 4th order was designed in TSMC 130nm CMOS technology. The fabricated front-end was designed for 160ns of peaking time, sensitivity of 30mV/fC and Equivalent Noise Charge (ENC) of 428e. The measured power consumption of the CSA and of the pulse shaper were 3.3mW and 4.2mW, respectively.

Fully integrated boost converter for thermoelectric energy harvesting

In this paper, a full integrated boost converter that allows energy extraction from low voltage thermoelectric generators. The converter uses a 22nH integrated metal-track inductor without external components and provide a 1.1V regulated output voltage from 300mV of input voltage and 45% of maximum efficiency in normal operation. In startup mode, the proposed architecture utilized a dickson charge-pump to pre-charge the output capacitor until control circuit can operate. The presented circuit was simulated and fabricated in 0.18um CMOS tecnology. The core occupies an area of about 0.7mm×0.9mm, without Pads.

On-chip 4to20mA reconfigurable current loop transmitter for smart sensor applications

An on-chip 4to20mA reconfigurable current loop transmitter with four input channels for remote smart sensor applications is presented. The designed system includes: a like-HART protocol based on frequency-shift keying modulator (FSK) and demodulator to an efficient communication in industrial environment, a power management sub-system, a standard 4to20mA output and an embedded NVM memory (256 bytes) for calibration and identification purposes. The integrated circuit was fabricated in standard 0.6um CMOS technology occupying an área of 11.1mm2.

Current mode 1.2-Gbps SLVS transceiver for readout front-end ASIC

This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes a feedback control which reduces the common-mode voltage variations in terms of the Vds voltage of the bias transistor, and an enable/disable operation mode, which minimizes the power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to design the receiver circuit being robust to transient common-mode variations with low power consumption and high speed. The experimental DC power consumption of the transceiver is 4.6 mW at 1.25V power supply, where 1.1 mW is consumed by the receiver and 3.5 mW by the transmitter. The eye diagram proves the proper dynamic operation of the circuit until a data rate of 1.2Gbps.

A 3.9 compression-ratio Huffman encoding scheme for the large ion collider on 65nm and 130nm CMOS technologies

A Huffman coding scheme with 3.9 compression ratio for the Large Hadron Collider experiment is proposed. A fully-synthesized scheme draws a small footprint layout of 60μm × 60μm in 65nm and 105μm × 105μm in 130nm CMOS process. The maximum operation frequencies are 435MHz for 65nm and 333MHz for 130nm, whereas the power consumption is 1.2mW and 1.9mW respectively. The resulting scheme enables a front-end electronics without any loss of data.

DPA insensitive voltage regulator for contact smart cards

An on-chip voltage regulator for contact smart cards in CMOS technology is presented. The proposed regulator protects the supplied system against power analysis attacks using a charge pump architecture to eliminate the power consumption correlation. It generates a 1.55V output from 1.65V to 5.5V input voltage. The circuit has been sized to handle a 50mA load current step with less than 250mV of voltage ripple without external capacitors. Thus, it can be applied in A, B and C classes of smart cards. The presented circuit was designed in a 0.18μm CMOS technology. The core occupies an area of about 0.15mm2, without Pads.