Richard Egloff

Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors

The dependence of avalanche breakdown voltage on the drift region length and buried oxide thickness of thin silicon-on-insulator (SOI) LDMOS transistors is reported. An ideal relationship between breakdown voltage and drift length is derived. Experimental SOI LDMOS transistors with near ideal breakdown voltages in the short-drift-length regime have been realized. Specifically, 380 V was achieved in a drift length of 20 mu m. Thin buried oxides are shown to be a major cause of deviation from this ideal. Experimental results verify this finding. An 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported.<<ETX>>

High performance 600 V smart power technology based on thin layer silicon-on-insulator

A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiCMOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 /spl mu/m-thick, with buried oxide layers in the range of 2.0 to 3.0 /spl mu/m-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SOI active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific on-resistance over conventional LDMOS structures for a given breakdown voltage.

Evaluation of wafer bonding and etch back for SOI technology

Abstract Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the original bulk Si quality in the superficial Si layer of such SOI structures have been investigated. Utilizing transmission x-ray topography combined with transmission electron microscopy (TEM), the critical processing parameters causing defect generation have been identified and the principal mechanisms of dislocation nucleation have been elucidated. Strain compensated bonded SOI wafers have also been evaluated by non-destructive elastic light scattering and optical beam induced current (OBIC) to obtain topographic defect maps of entire SOI wafers. This analytical technique has the capability to comprehensively characterize surface and subsurface morphological features which result from the bonding and thinning processing steps. A comparison of wafer bonding and etch back technology with different etch stop fabrication techniques is presented. In this review, it is demonstrated that the presence of a boron-doped etch stop layer, with its accompanying lattice contraction and strain compensation, represents a key difference in the observed morphological patterns of bonded SOI wafers.

EVALUATION OF STRAIN SOURCES IN BOND AND ETCHBACK SILICON-ON-INSULATOR

Abstract The incorporation of strain is inherent in the manufacture of bond and etchback silicon-on-insulator (BESOI) substrates. In this paper, the principal sources of strain are identified and the magnitude of the strain is estimated. The strain sources discussed include dopant (boron) induced lattice contraction of the etchstop layer, differential thermal expansion, and interfacial microroughness at the time of bonding. Reduction or elimination of SOI layer degradation from some of these strain sources is possible.

600 V single-chip power conversion system based on thin layer silicon-on-insulator

Summary form only given. An integrated 600 V power conversion circuit is described based on smart power technology which combines novel lateral high-voltage RESURF transistor structures and a merged bipolar/CMOS/DMOS process flow on thin-layer SOI substrates. A modular process flow provides for the integration of half-bridge power stages along with level shifting and lowand medium-voltage control. This opens new application areas for thin-layer SOI, such as lighting electronics, power modules, motor control, etc., and is a significant development for the integration of power conversion systems.