S. Merchant

Realization of high breakdown voltage (>700 V) in thin SOI devices

The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip.<<ETX>>

Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors

The dependence of avalanche breakdown voltage on the drift region length and buried oxide thickness of thin silicon-on-insulator (SOI) LDMOS transistors is reported. An ideal relationship between breakdown voltage and drift length is derived. Experimental SOI LDMOS transistors with near ideal breakdown voltages in the short-drift-length regime have been realized. Specifically, 380 V was achieved in a drift length of 20 mu m. Thin buried oxides are shown to be a major cause of deviation from this ideal. Experimental results verify this finding. An 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported.<<ETX>>

Comparison of junction-isolated and soi high-voltage devices operating in the source-follower mode

Recent developments in high-voltage devices have made it feasible to realize monolithic power integrated circuits that combine high voltage devices with control, level shifter and logic function on a single chip. One of the important uses of such circuits is to assemble bridge circuits, which are needed whenever waveforms of arbitrary shape and frequency have to be synthesized. Typical examples are electronic ballasts and motor drives. In such circuits the source of the upper of the two switches, the high-side transistor, has to float above ground potential. In this work we have studied, both theoretically and experimentally, the behavior of junction-isolated (JI) and silicon-on-insulator (SOI) devices in applications involving the source-follower configuration at voltages up to 700 V. We find that the SO1 devices exhibit significantly lower on-resistance under source-high conditions than do JI devices, and that this effect is especially pronounced at high source bias voltages. The devices used in this study were LDMOS transistors, with off-state breakdown voltages of 500-700V (Fig. 1). Both types of devices were designed according to the RESURF principle in order to maximize the breakdown voltage [l, 21. Measurements of the on-state Id - Vh characteristic of the JI transistor in common-source and source-high configurations indicate that, in the latter case, the difference between the substrate and source potentials causes the drift region of the LDMOS transistor to become depleted, resulting in an increase of the on-resistance. In the case of the the SO1 device, however, an inversion layer forms at the buried oxide-SO1 layer interface. Once strong inversion is established, the width of the depletion region does not increase with further increase in the substrate potential, so that the remainder of the SO1 layer remains undepleted. Consequently, relatively little change occurs in the on-resistance of the SO1 device after the initial onset of the inversion layer. As a consequence of the RESURF principle which imposes conditions on the drift region charge, the specific on-resistances of the JI and SO1 devices in common-source configuration are comparable. However, as the source potential increases, the SO1 on-resistance increases slightly and saturates to a constant value, while the on-resistance of the JI device increases much more drastically (Fig. 2). This effect in JI devices can be alleviated to some extent by design modifications, such as the use of a lightly-doped substrate, a thicker epitaxial layer or inclusion of additional charge-compensating regions [3]. However, the effectiveness of such modifications at very high voltages is limited. For this reason, the source-follower operation becomes more difficult to realize in very-high- breakdown-voltage JI devices. This behavior has important implications on the ability to integrate high-voltage source-follower devices in power integrated circuits. The substantial increase in the on-resistance of the JI transistor would necessitate a correspondingly large increase in the device area, making the integration impractical. Such a limitation does not exist in the SO1 technology, which is thus more suitable for integrating multiple power devices on a single chip.

High-temperature performance of SOI and bulk-silicon RESURF LDMOS transistors

High-temperature off-state and on-state characteristics of bulk-Si and thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically. The off-state leakage current in the SOI devices was only 1.5 nA//spl mu/m at 300/spl deg/C. The increase of on-resistance with temperature in the SOI devices is smaller than in the bulk-Si devices because of the heavier doping dictated by the RESURF principle. The reverse recovery time of the SOI device shows only slight temperature dependence. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications.

Tunneling in thin SOI high voltage devices

Tunneling of electrons from valence to conduction band in thin SOI high voltage devices is reported for the first time. A close correlation between the theoretical and experimental reverse leakage current in 600-700 V thin SOI diodes is shown, including buried oxide thickness dependence, substrate bias dependence, and temperature dependence. Band-to-band tunneling is also verified with numerical simulation.

High-breakdown-voltage devices in ultra-thin SOI

The possible advantages of an SOI (silicon-on-insulator) RESURF (reduced surface electric field) device are explored with an idealized lateral diode structure consisting of a P/sup +/ diffusion into an N-silicon-on-insulator film, supported by an N/sup +/ silicon substrate. An optimized structure is shown to have a uniform lateral electric field and a vanishing vertical electric field along the top surface of the depletion region. An analytical model based on ionization integrals indicates that, for very thin SOI, the breakdown voltage increases with decreasing SOI thickness. Two-dimensional numerical breakdown simulations also support this finding. Experimentally, breakdown voltages in excess of 700 V have been demonstrated on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers, in excellent agreement with theory. An obvious advantage of this concept lies in the integration of high-voltage devices with high-performance SOI CMOS circuits on a single chip.<<ETX>>