Enrico Monaco

A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves

Wireless on-chip processing at millimeter waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased-array systems, frequency division with an operating range wide enough to compensate spreads due to component variations. This paper addresses the implementation of these functions, introducing new circuit solutions. The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56-60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW.

A mm-Wave quadrature VCO based on magnetically coupled resonators

Wireless signal processing at mm-Waves would benefit from the availability of a quadrature signal reference, enabling direct-conversion transceiver architectures and providing phase rotators drivers in phased arrays systems [1]. They are furthermore attractive for clock recovery in ICs for wireline applications. Search of a compact quadrature generator at around 60GHz with low phase noise at moderate power is the topic of this work. Discarding a double-frequency VCO followed by dividers-by-two given the high frequency range of operation, the most suitable topology borrowed by RF solutions is represented by cross-coupled LC voltage-controlled oscillators [2]. However, the oscillation frequency dependence on the biasing current makes it susceptible to phase noise, close-in in particular [3]. At mm-Waves, this is exacerbated by core devices of small dimensions to such an extent that 1/f3 noise remains dominant up to more than ∼10MHz, making it unsuitable for stringent applications. On the contrary a ring of two VCOs magnetically coupled to each other, as shown in Fig. 16.2.1, has an oscillation frequency dependence on inter-stage passive components only, low 1/f3 noise together with good quadrature accuracy. The quadrature oscillator has been realized in a 65nm CMOS technology and prototypes show the following performances: 56-to-60.3GHz tunable oscillation frequency, phase noise better than −95dBc/Hz at 1MHz offset in the tuning range, 1.5° maximum phase error while consuming 22mA from a 1V supply.

A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension

Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due to process variations and the stringent reference phase noise to ensure signal integrity calls for an ultra-wide tuning range and low-noise on-chip oscillator. Meeting this target is even more challenging when adopting an ultra-scaled CMOS technology node where key passive components suffer from a reduced quality factor (Q) [1]. In a 32nm node the thickness of metals closer to the substrate is half that in a 65nm process leading, for example, to MOM capacitors with roughly half Q. The penalty is only marginally compensated by the higher transistor ft, improved only by ~20%. Various techniques exploiting alternative tuning implementations have been published recently. Magnetic tuning methods where the equivalent tank inductance is varied through reflection of the secondary coil impedance of a transformer demonstrate outstanding tuning ranges but at the cost of a severe trade-off with tank Q and poor noise FOMs [2,3]. A bank of capacitors switched in and out in an LC tank is the most popular tuning approach [4-6]. However the quality factor is severely degraded, when large ranges are involved. In this work, the switched-capacitor tank of the VCO shown in Fig. 20.3.1 is centered around two different resonance frequencies by splitting the inductor through the switch Msw. In particular, an up-shift is produced when the switch is off due to its parasitic capacitance. The frequency range is significantly increased without compromising tank Q leading to large tuning range and high FOM simultaneously. Prototypes of the VCO have been realized in 32nm CMOS showing the following performances: 31.6% frequency tuning range, minimum phase noise of -118dBc/Hz at 10MHz offset from 40GHz with 9.8mW power dissipation. Despite being realized in an ultra-scaled 32nm standard digital CMOS process without RF thick metal options, the oscillator shows state-of-the-art performances.

A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms [1,2]. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers, working as dynamic CML latches, to realize high speed and low power mm-Wave dividers. The solution is very compact, which is particularly desirable at mm-Waves to ease chip layout and shorten IC interconnections, minimizing signal losses. A frequency divider-by-4 has been realized in a 65nm bulk CMOS technology and prototypes prove an operating frequency programmable from 20 to 70GHz. The frequency range in each sub-band spans from 10% to 17%, corresponding to a 2.5x to 4x improvement compared to injection-locked dividers-by-4. Maximum power dissipation is 6.5mW and occupied area is only 15μm × 30μm.

A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output

Frequency multipliers in CMOS are key blocks in new emerging applications at μ-waves and mm-waves. Classical solutions, in bipolar technology, exploit the steep non-linear I–V characteristic in order to generate output harmonics at multiples of the input signal frequency. This solution would lead to a very limited gain (or even loss) in CMOS. In this paper we propose a novel circuit topology where a differential pair, in push-push configuration, locks an LC oscillator over a wide frequency range. A behavioral model of the circuit is presented and simple design equations for locking range and output swing are derived. Prototypes, realized in a standard 0.13μm CMOS technology, show 30% locking range around 13GHz with 3dBm input power. Suppression of the unwanted input signal and its 3rd harmonic is better than 45dBc. Core power dissipation is 5.2mW only, less than half compared with state of the art.

A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output

A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.

6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI

Electrical link migration requires serial interfaces to operate at increasing data rates. Despite the fact that most standards still employ NRZ, practical signal integrity constraints demand PAM-4 modulation, especially for some interconnect applications and low-loss profiles [1]. Nevertheless, compared to NRZ, the design of high-speed PAM-4 transmitters entails several challenges. Achieving high linearity without reducing the output amplitude is key to preserve high SNR, which is tightened by the intrinsic 1/3 eye amplitude reduction. Moreover, transitions between non-adjacent levels reduce horizontal eye openings, demanding wide bandwidth and tight timing constraints. In light of the above issues, pushing the transmitter to high data-rates while maintaining signal integrity and energy efficiency is challenging. In fact, published PAM-4 transmitters [2–5] do not meet the CEI-56G-PAM4 standard [1], requiring up to 56Gb/s and 4-taps of feedforward equalization (FFE). To reach the target, improvements on both the architecture and the circuit side are required. A serializer architecture is presented in this paper. To save power, clocking signals are generated and distributed at quarter-rate, but the last stage employs 2∶1 multiplexers (MUXs) driven by half-rate clocks generated locally to overcome the speed limitation of 4∶1 MUXs. Moreover, a new current-mode driver allows high swing and good linearity by raising the power supply without compromising speed and reliability, and a double T-coil splits transistors and ESD parasitics to meet the bandwidth requirements for the target data rate.

A 5mW CMOS wideband mm-wave front-end featuring 17dB of conversion gain and 6.5 dB minimum NF

The low quality factor of passive components at mm-wave limits the impedance magnitude of resonators and leads to poor current to voltage conversion in amplifiers. To achieve significant LNA gain at mm-wave, multiple stages are required with the consequence of large power dissipation. Delaying the current to voltage conversion at intermediate frequency while processing the mm-wave signal in current domain is pursued in this work. LNA and mixer are merged in a single stage and show an overall front-end noise figure comparable to state of the art CMOS standalone LNAs. In view of integration of large phased arrays for wireless data transfers at Gbit/s, the solution offers the key advantage of an extremely low power consumption together with a very low occupied area. Test chips realized in 65nm CMOS, show the following performances: 48GHz to 62GHz input frequency range, conversion gain of 17dB and minimum noise figure of 6.5dB when translating the signal to an intermediate frequency of 18.5GHz. Power dissipation and die area are 5mW and 320 × 170 μm2 only. Normalizing performances by means of the usually adopted figure of merit for LNAs, the proposed front-end outperforms all recently published CMOS LNAs while providing both amplification and frequency translation.

The Impact of CMOS Scaling on the Design of Circuits for mm-Wave Frequency Synthesizers

Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this article is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65 and 32 nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. fT and fMAX increase though slower than in the past, ron*Coff, a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32 nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108 GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes.

A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of