Enrique San Andrés

High- k gate stacks on low bandgap tensile strained Ge and GeSn alloys for field-effect transistors

We present the epitaxial growth of Ge and Ge0.94Sn0.06 layers with 1.4% and 0.4% tensile strain, respectively, by reduced pressure chemical vapor deposition on relaxed GeSn buffers and the formation of high-k/metal gate stacks thereon. Annealing experiments reveal that process temperatures are limited to 350 °C to avoid Sn diffusion. Particular emphasis is placed on the electrical characterization of various high-k dielectrics, as 5 nm Al2O3, 5 nm HfO2, or 1 nmAl2O3/4 nm HfO2, on strained Ge and strained Ge0.94Sn0.06. Experimental capacitance-voltage characteristics are presented and the effect of the small bandgap, like strong response of minority carriers at applied field, are discussed via simulations.

Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around , implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents.

Optimization of in situ plasma oxidation of metallic gadolinium thin films deposited by high pressure sputtering on silicon

Gadolinium oxide thin films were deposited on silicon by a two-step process: high pressure sputtering from a metallic gadolinium target followed by an in situ plasma oxidation. Several plasma conditions for metal deposition and oxidation were studied in order to minimize the growth of a SiOx layer at the interface between the high permittivity dielectric and the silicon substrate and to avoid substrate damage. Plasma emission was studied with glow discharge optical spectroscopy. The films were structurally characterized by Fourier transform infrared spectroscopy. Metal–insulator–semiconductor capacitors were fabricated with two different top metals (titanium and platinum) to analyze the influence of deposition conditions and the metal choice. Pt gated devices showed an interfacial SiOx regrowth after a forming gas annealing, while Ti gates scavenge the interface layer.

Interface quality of Sc2O3 and Gd2O3 films based metal–insulator–silicon structures using Al, Pt, and Ti gates: Effect of buffer layers and scavenging electrodes

In this work, the electrical characterization of Gd2O3 and Sc2O3-based metal–insulator–silicon (MIS) structures has been performed using capacitance–voltage, deep level transient spectroscopy, conductance transients, flat-band voltage transients, and current–voltage techniques. High-k films were deposited by high pressure sputtering using Sc and Gd metallic films in a pure Ar plasma and, subsequently, in situ room temperature plasma oxidation in a mixed Ar/O2 atmosphere was performed. Three different metals were used as gate electrodes: aluminium, platinum, and titanium, in order to check electrical differences of the samples and to check the interface scavenging after high-k dielectric deposition. In particular, it was proved that Ti electrode is a well SiO2 interlayer scavenger for both materials. Additionally, the authors observed that the predominant conduction mechanism for these high-k based-MIS structures is Poole–Frenkel emission, as usually reported for high-k dielectrics.

Optimization of gadolinium oxide growth deposited on Si by high pressure sputtering

High κ gadolinium oxide thin layers were deposited on silicon by high-pressure sputtering (HPS). In order to optimize the properties for microelectronics applications, different deposition conditions were used. Ti (scavenger) and Pt (nonreactive) were e-beam evaporated to fabricate metal–insulator–semiconductor (MIS) devices. According to x-ray diffraction, x-ray photoelectron spectroscopy, and Fourier-transform infrared spectroscopy, polycrystalline stoichiometric Gd2O3 films were obtained by HPS. The growth rate decreases when increasing the deposition pressure. For relatively thick films (40 nm), a SiOx interface as well as the formation of a silicate layer (GdSiOx) is observed. For thinner films, in Ti gated devices the SiOx interface disappears but the silicate layer extends over the whole thickness of the gadolinium oxide film. These MIS devices present lower equivalent oxide thicknesses than Pt gated devices due to interface scavenging. The density of interfacial defects Dit is found to decrease wi...

High pressure sputtering as a viable technique for future high permittivity dielectric on III-V integration: GdOx on InP demonstration

The electrical properties of metal–oxide–semiconductor devices based on GdOx obtained by high pressure sputtering on InP substrates are studied. In order to prevent damage of the semiconductor substrate, an optimized two-step sputtering procedure has been used for the high permittivity dielectric deposition. First, a thin metallic Gd film was sputtered using a metallic Gd target and a pure Ar plasma. Then, without extracting the sample from the system, the GdOx films were obtained by plasma oxidation using an Ar/O2 mixed atmosphere and reducing plasma power to minimize damage and interfacial regrowth. The resulting devices show fully functional capacitance curves. After forming gas annealing, the capacitors do not show interface regrowth up to a temperature of 500 °C and the gate leakage stays within reasonable limits, below 2 × 10−4 Acm−2 at a gate voltage of 1.5 V. In addition, the interface trap density remains roughly constant with annealing temperature up to 400 °C, in the low 1013 eV−1cm−2 range, de...

High-k Characterization by RFCV

High-k characterization by RFCV E. San Andres, L. Pantisano, Ph. J. Roussel, M. Toledano-Luque, L. Trojman, S. Severi, S. DeGendt, G.Groeseneken. Universidad Complutense de Madrid, Electricity and Electronics Dept., Spain. IMEC, Leuven, Belgium. KULeuven, Dept. of Chemistry, Leuven, Belgium. KULeuven ESAT, Leuven, Belgium. Introduction The aggressive scaling down of microelectronic devices is pushing for the SiO2 gate dielectric replacement by novel higher-k dielectrics, to realize the further decrease of the equivalent oxide thickness (EOT) to the sub-1nm range. However, the chemical stability and/or process compatibility of these dielectrics is not guaranteed. Also, due to the low thickness normally they present high gate leakages due to tunneling. Thus novel measurement techniques have to be adopted to asses their quality. This paper addresses some recent developments on RF-CV characterization to quantify basic parameters like EOT, mobility and Vth in the short and leaky MOSFET devices of interest for sub-32nm technologies. Robust gate parameter extraction A decrease in the gate oxide thickness leads to an exponential increase in gate tunneling current. Assessment of the gate capacitance with standard CV setups becomes very unreliable for Jg>100A.cm (appearance of the well known capacitance “roll-off” [1]). Increasing the frequency (RFCV) alleviates this problem at the cost of increased complexity [2] (RF compatible devices, high frequency probes, bondpad deembedding, etc.). Further, when the leakage is extremely large the parameter extraction from the measured impedance is still challenging. An accurate parameter extraction procedure with leakage up to 1000A.cm is shown in Fig.1. Using a 2step robust automated procedure [3] the gate impedance parameters of the standard 3 lumped elements model (Fig. 1A) can be reliably obtained, without needing to complicate the model. A first estimation of Rseries and RDT comes from the circle fit of Im[Z] vs Re[Z] (Fig. 1B) and in a second step Z is fitted to the 3-parameter model (Fig 1C), including Cgate. This 2-step procedure avoids uncertainties due to instrument inaccuracies or poor parameter fitting procedures. Cg-V curves for state of the art 0.78 nm HfO2 devices with leakage in excess of 1000A.cm are shown in fig. 1D. RF-split-CV measurement Conventional RF-CV measurements can only measure Cga (gate-to-all capacitance), but the use of an optimized layout further allows the quantification of the gate-to-channel capacitance (i.e. split-CV[4]). Carrier separation can be done at high frequencies using a 2-port vector network analyzer [5]. This RF-split-CV opens the path to extend conventional extraction like inversion capacitance or channel mobility to the sub-1nm EOT range. When the leakage is low or moderate both split techniques yield the same results, but for high leakage conventional split-CV fails while RF-split-CV results remain correct (Fig. 2). Mobility determination RF-split-CV measurements permit the accurate Cgc and Cgb measurement. These capacitances are affected by large parasitics due to fringe field effects. The measurement of devices with several gate lengths, together with SEM/SSRM measurements permits very accurate extraction of the effective channel length, relying on electrical measurements only, without needing further assumptions (unlike e.g. the shift-andratio method [6]). This way the parasitic capacitances can be determined [7]. Coupling these RF-split-CV results with conventional Id-Vg measurements [8] enables accurate mobility determination in very short devices (Fig. 3 shows results for leaky HfSiON devices, with channel lengths down to 81 nm and EOT as low as 1nm). References [1] C-H. Choi et al. IEEE Elect. Dev. Lett. 20 (1999) 292. [2] J. Schmitz et al. IEEE Elect. Dev. Lett. 24, (2003) 37. [3] E. San Andres et al. IEEE Trans. on Elect. Dev. Accepted for publication. [4] C.G. Sodini, et al Solid-State Elect. 25 (1982) 833. [5] E. San Andres et al. IEEE Elect. Dev. Lett. 27 (2006), 772. [6] Y. Taur et al. IEEE Elect. Dev. Lett. 13 (1992) 267. [7] E. San Andres et al. Mic. Eng. 84 (2007), 1162. [8] S. Severi et al. IEEE Trans. on Elect. Dev. Accepted for publication.

Conductance Transient Comparative Analysis of Electron-Cyclotron Resonance Plasma-Enhanced Chemical Vapor Deposited SiNx, SiO2/SiNx and SiOxNy Dielectric Films on Silicon Substrates

An interface quality comparative study of metal-insulator-semiconductor (MIS) structures based on SiNx, SiO2/SiNx and SiOxNy dielectric films deposited on silicon substrates by electron-cyclotron resonance plasma-enhanced chemical vapor deposition (ECR-PECVD) has been carried out. Overall interpretation of deep-level transient spectroscopy (DLTS) and conductance transient (G-t) measurements enables us to conclude that the interface quality of Al/SiOxNy/Si MIS structures is superior to those of Al/SiNx/Si devices. Moreover, we have proved that thermal treatments applied to Al/SiOxNy/Si capacitors induce defect passivation, possibly related to the presence of hydrogen in the films, and disorder-induced gap-state (DIGS) density maxima can decrease to values even lower than those corresponding to Al/SiNx/SiO2/Si devices.

Gadolinium scandate by high pressure sputtering as a high-k dielectric

We demonstrate the viability of gadolinium scandate (Gd_2-xSc_xO₃) deposition by high pressure sputtering from targets of its binary compounds (gadolinium and scandium oxides), followed by an anneal in forming gas. Pt/8 nm Gd_2-xSc_xO₃/n-Si MIS devices were fabricated and characterized. Gadolinium scandate is found to be more stable than ScO_x and GdO_x in contact with Si. These three dielectrics show a high quality interface, with low leakage currents.

Electrical study of ScO-based MIS structures using Al and Ti as gate electrodes

The electrical properties of ScO-based MIS structures have been electrically studied. The high-k films were deposited by high pressure sputtering (HPS). Aluminum and Ti were used as gate electrodes. Defects inside the oxide seem to be reduced when increasing the chamber pressure. However, leakage current density increases in this case.