P. C. Feijoo

Scandium oxide deposited by high-pressure sputtering for memory devices: Physical and interfacial properties

Scandium oxide (ScO(x)) thin layers are deposited by high-pressure sputtering (HPS) for physical and electrical characterization. Different substrates are used for comparison of several ScO(x)/Si interfaces. These substrates are chemical silicon oxide (SiO(x)), H-terminated silicon surface and silicon nitride (SiN(x)), obtained by either electron-cyclotron-resonance chemical vapor deposition or plasma enhanced nitridation of the Si surface. Transmission electron microscopy images show that a 1.7 nm thick SiO(x) layer grows when ScO(x) is deposited on H-terminated silicon surface. We demonstrate that interfacial SiN(x) has some advantages over SiO(x) used in this work: its permittivity is higher and it presents better interface quality. It also avoids Si oxidation. An improvement of one order of magnitude in the minimum of interface trap density is found for SiN(x) with respect to the SiO(x), reaching values below 2 x 10(11) cm(-2) eV(-1). HPS deposited ScO(x) films are polycrystalline with no preferential growth direction for the used deposition conditions and their properties do not depend on the substrate. This material could be a candidate for high-k material in flash memory applications.

Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around , implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents.

Optimization of in situ plasma oxidation of metallic gadolinium thin films deposited by high pressure sputtering on silicon

Gadolinium oxide thin films were deposited on silicon by a two-step process: high pressure sputtering from a metallic gadolinium target followed by an in situ plasma oxidation. Several plasma conditions for metal deposition and oxidation were studied in order to minimize the growth of a SiOx layer at the interface between the high permittivity dielectric and the silicon substrate and to avoid substrate damage. Plasma emission was studied with glow discharge optical spectroscopy. The films were structurally characterized by Fourier transform infrared spectroscopy. Metal–insulator–semiconductor capacitors were fabricated with two different top metals (titanium and platinum) to analyze the influence of deposition conditions and the metal choice. Pt gated devices showed an interfacial SiOx regrowth after a forming gas annealing, while Ti gates scavenge the interface layer.

Scavenging effect on plasma oxidized Gd2O3 grown by high pressure sputtering on Si and InP substrates

In this work, we analyze the scavenging effect of titanium gates on metal-insulator-semiconductor capacitors composed of gadolinium oxide as dielectric material deposited on Si and InP substrates. The Gd2O3 film was grown by high pressure sputtering from a metallic target followed by an in situ plasma oxidation. The thickness of the Ti film was varied between 2.5 and 17 nm and was capped with a Pt layer. For the devices grown on Si, a layer of 5 nm of Ti decreases the capacitance equivalent thickness from 2.3 to 1.9 nm without compromising the leakage current (10−4 A cm−2 at Vgate = 1 V). Thinner Ti has little impact on device performance, while 17 nm of Ti produces excessive scavenging. For InP capacitors, the scavenging effect is also observed with a decrease in the capacitance equivalent thickness from 2.5 to 1.9 nm (or an increase in the accumulation capacitance after the annealing from ~1.4 to ~1.7–1.8 μF cm−2). The leakage current density remains under 10−2 A cm−2 at Vgate = 1.5 V. For these devices, a severe flatband voltage shift with frequency is observed. This can be explained by a very high interface trap state density (in the order of 1013–1014 eV−1 cm−2).

Interface quality of Sc2O3 and Gd2O3 films based metal–insulator–silicon structures using Al, Pt, and Ti gates: Effect of buffer layers and scavenging electrodes

In this work, the electrical characterization of Gd2O3 and Sc2O3-based metal–insulator–silicon (MIS) structures has been performed using capacitance–voltage, deep level transient spectroscopy, conductance transients, flat-band voltage transients, and current–voltage techniques. High-k films were deposited by high pressure sputtering using Sc and Gd metallic films in a pure Ar plasma and, subsequently, in situ room temperature plasma oxidation in a mixed Ar/O2 atmosphere was performed. Three different metals were used as gate electrodes: aluminium, platinum, and titanium, in order to check electrical differences of the samples and to check the interface scavenging after high-k dielectric deposition. In particular, it was proved that Ti electrode is a well SiO2 interlayer scavenger for both materials. Additionally, the authors observed that the predominant conduction mechanism for these high-k based-MIS structures is Poole–Frenkel emission, as usually reported for high-k dielectrics.

Optimization of gadolinium oxide growth deposited on Si by high pressure sputtering

High κ gadolinium oxide thin layers were deposited on silicon by high-pressure sputtering (HPS). In order to optimize the properties for microelectronics applications, different deposition conditions were used. Ti (scavenger) and Pt (nonreactive) were e-beam evaporated to fabricate metal–insulator–semiconductor (MIS) devices. According to x-ray diffraction, x-ray photoelectron spectroscopy, and Fourier-transform infrared spectroscopy, polycrystalline stoichiometric Gd2O3 films were obtained by HPS. The growth rate decreases when increasing the deposition pressure. For relatively thick films (40 nm), a SiOx interface as well as the formation of a silicate layer (GdSiOx) is observed. For thinner films, in Ti gated devices the SiOx interface disappears but the silicate layer extends over the whole thickness of the gadolinium oxide film. These MIS devices present lower equivalent oxide thicknesses than Pt gated devices due to interface scavenging. The density of interfacial defects Dit is found to decrease wi...

Electrical and chemical characterization of high pressure sputtered scandium oxide for memory applications

Scandium oxide was deposited by means of high pressure sputtering in the same conditions on differently prepared (100) Si substrates: chemical oxide, nitrided Si and deposited silicon nitride. Time-of-flight secondary ion mass spectroscopy and X-ray photoemission spectroscopy show that polycrystalline Sc2O3 films were grown with a composition which is constant with depth. According to Capacitance-Voltage hysteresis measurements, nitrided Si or deposited SiNx proved to present a lower density of defects in the interface as compared to RCA native oxide.

Gadolinium scandate by high-pressure sputtering for future generations of high-κ dielectrics

Gd-rich gadolinium scandate (Gd2–xScxO3) was deposited by high-pressure sputtering on (1 0 0) silicon by alternating the deposition of <0.5 nm thick films of its binary components: Sc2O3 and Gd2O3. The formation of the ternary oxide was observed after the thermal treatments, with a high increase in the effective permittivity of the dielectric (up to 21). The silicon diffuses into the Gd2–xScxO3 films, which show an amorphous character. After the annealing no interfacial silicon oxide is present. CHF–VG curves indicated low hysteresis (55 mV) and a density of interfacial defects of 6 × 10 11 eV –1 cm –2 . (Some figures may appear in colour only in the online journal)

High pressure sputtering as a viable technique for future high permittivity dielectric on III-V integration: GdOx on InP demonstration

The electrical properties of metal–oxide–semiconductor devices based on GdOx obtained by high pressure sputtering on InP substrates are studied. In order to prevent damage of the semiconductor substrate, an optimized two-step sputtering procedure has been used for the high permittivity dielectric deposition. First, a thin metallic Gd film was sputtered using a metallic Gd target and a pure Ar plasma. Then, without extracting the sample from the system, the GdOx films were obtained by plasma oxidation using an Ar/O2 mixed atmosphere and reducing plasma power to minimize damage and interfacial regrowth. The resulting devices show fully functional capacitance curves. After forming gas annealing, the capacitors do not show interface regrowth up to a temperature of 500 °C and the gate leakage stays within reasonable limits, below 2 × 10−4 Acm−2 at a gate voltage of 1.5 V. In addition, the interface trap density remains roughly constant with annealing temperature up to 400 °C, in the low 1013 eV−1cm−2 range, de...

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO2/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-j oxide than in the sidewall of the fin. This could explain more severe PBTI degradation. 2011 Elsevier Ltd. All rights reserved.