M. Cases

Finite-difference modeling of noise coupling between power/ground planes in multilayered packages and boards

Multilayered packages and boards, such as high performance server boards, contain thousands of signal lines, which have to be routed on and through several layers with power/ground planes in between. There can be noise coupling not only in the transversal direction through the power/ground planes in such a structure, but also vertically from one plane pair to another through the apertures and via holes. In addition, the continuous increase in power demand along with reduced Vdd values results in significant current requirement for the future chips. Hence, the parasitic effects of the power distribution system become increasingly more critical regarding the signal integrity and electromagnetic interference properties of cost-effective high-performance designs. We present a multilayer finite-difference method (M-FDM), which is capable of characterizing such noise coupling mechanisms. This method allows considering realistic structures, which would be prohibitive to simulate using full-wave simulators

IBM BladeCenter system electrical packaging design challenges

This work describes the electrical and thermal design challenges encountered during the definition, design and verification of a BladeCenter/spl trade/ system configuration utilizing high speed serial signal interfaces. This system uses gigabit Ethernet (GbE), fiber channel (FC) and Infiniband (IB) interfaces for interconnecting processor blades through high speed cross-bar switches with built-in redundancy capability. A comprehensive electrical design methodology including accurate and detailed modeling and simulation of the complete design space is required to achieve the speeds provided by these standard interfaces using low-cost printed circuit board material. The focus of the analysis is on the link attenuation for the system described. The cooling solution needed to accommodate the overall system thermal requirement for maximum configuration is also discussed.

Massively parallel conformal FDTD on a BlueGene supercomputer

This paper presents modeling and simulation utilizing a parallel conformal finite difference time domain (PFDTD) (Wenhua Yu, 2003) code developed at the Electromagnetic Communication (EMC) Laboratory of Pennsylvania State University on a massively parallel supercomputer. Parallelization, scalability, and application to the modeling of high-end server electrical interconnects is examined.

Design and packaging challenges for on-board cache subsystems using source synchronous 400 Mb/s interfaces

This paper describes circuit and packaging design challenges encountered while attempting to optimize the source synchronous timing equations for the system level interconnects using a 200 MHz double data rate (DDR) level 3 (L3) cache subsystem. Various solutions to these challenges are presented. The delay skew budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated delay skew control techniques.

Neuro-genetic models in modeling nonlinear digital I/O buffer circuits

Neural network models are used as strong interpolation tools to model digital I/O buffer circuits accurately. Training a neural network involves use of complex training algorithms. Optimizing a neural network is complicated due to a large number of variable parameters involved in the process. Genetic algorithms are used to optimize a problem with a very large number of possible solutions as they can quickly find a near optimal solution without having to do an exhaustive search of the solution space. In this paper, a methodology based on genetic algorithms is proposed to optimize a neural network model to accurately capture the nonlinearity of digital driver circuits. The proposed methodology is tested on IBM driver circuits and results show significant improvement in the accuracy of the neural network model.

Voltage regulator module noise analysis for high-volume server applications

This paper presents a methodology to analyze voltage regulator module (VRM) noise coupling problems in high-volume server applications. The technique is applied on a real engineering design. The comprehensive model includes irregular power shapes, decoupling capacitors, and dielectric and conductive loss. Irregular shaped power plane modeling is cross-checked with four separate methods to demonstrate accuracy.

Macro-modeling of transistor level receiver circuits

A modeling methodology for macro-modeling transistor level receiver circuits has been proposed. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits i.e., the input characteristics of the receivers. In this work, the proposed modeling approach addresses both the loading effect of the receiver as well as the output characteristics of the receiver. The proposed modeling technique is simple, accurate and has huge computational speed-up over transistor level receiver circuits. A recurrent neural network (RNN) model is used to model the loading effect of the receiver. The output characteristics of the receiver is modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on a few test cases and results show good accuracy.

Macro-modeling of non-linear pre-emphasis differential driver circuits

Differential signaling has become important in high speed digital and mixed signal systems because of its numerous advantages over single-ended signaling. Differential signaling reduces effects like simultaneous switching noise (SSN), electro magnetic interference (EMI) and crosstalk coupling. Signal integrity (SI) and timing analysis using differential drivers is computationally exhaustive due to increased complexity in design that includes features such as pre-compensation and slew rate control. Therefore, accurate macro-modeling of differential driver circuits for a quality design is a huge challenge. In this paper, a modeling technique based on recurrent neural network (RNN) is proposed to model differential driver circuits with and without pre-emphasis. Good accuracy is obtained in the test cases shown for the proposed modeling methodology at minimum computational cost.

Data center server packaging technology

The purpose of this paper is to describe BladeCenter/spl trade/ packaging technology and compare with 1U and 2U rack systems to illustrate the improvements. The power and thermal design challenges are described. The paper covers in detail power and thermal design advantages, and overall cost performance compared to 1U servers. A blade server is a rack-optimized server architecture designed to include the benefits of standardized 1U rack systems while eliminating the complications associated with these systems. The term BladeCenter refers to a chassis that can hold a number of hot-swappable devices called blades server. A blade sever is an independent server containing one or more processors, memory, disk storage, and network controllers. The BladeCenter was created to simplify the deployment of servers in an enterprise infrastructure.

Scalable driver I/O macromodels for statistical analysis

In this paper, scalable driver I/O macromodels have been proposed for efficient signal integrity and timing analysis of todays high-speed systems. Variations in semiconductor process, temperature, and power supply voltage affect the output voltage and current in driver circuits. The effect of these variations on driver and receiver circuits has been captured using Lagranges interpolation technique. In this paper, scalable macromodeling approach has been applied to differential driver circuits and single-ended driver and receiver circuits. Scalable driver and receiver circuits consume less CPU memory and simulation time compared to transistor-level driver and receiver circuits. The accuracy of scalable macromodels has been tested on various test cases for differential driver and single-ended driver-receiver circuits and results yielded good accuracy.