N. Pham

IBM BladeCenter system electrical packaging design challenges

This work describes the electrical and thermal design challenges encountered during the definition, design and verification of a BladeCenter/spl trade/ system configuration utilizing high speed serial signal interfaces. This system uses gigabit Ethernet (GbE), fiber channel (FC) and Infiniband (IB) interfaces for interconnecting processor blades through high speed cross-bar switches with built-in redundancy capability. A comprehensive electrical design methodology including accurate and detailed modeling and simulation of the complete design space is required to achieve the speeds provided by these standard interfaces using low-cost printed circuit board material. The focus of the analysis is on the link attenuation for the system described. The cooling solution needed to accommodate the overall system thermal requirement for maximum configuration is also discussed.

Transmitter and channel equalization for high-speed server interconnects

As the demand for higher performance increases the operating frequencies, the complexity and sophistication of interface designs are increased to enable operation of high speed links in imperfect, lossy, and cost competitive environments. This paper investigates three equalization methods for high speed differential serial links: transmitter equalization, discrete equalization, and distributed cable equalization. The performance, advantages, and tradeoffs among the methods is examined.

Massively parallel conformal FDTD on a BlueGene supercomputer

This paper presents modeling and simulation utilizing a parallel conformal finite difference time domain (PFDTD) (Wenhua Yu, 2003) code developed at the Electromagnetic Communication (EMC) Laboratory of Pennsylvania State University on a massively parallel supercomputer. Parallelization, scalability, and application to the modeling of high-end server electrical interconnects is examined.

Massively Parallel Conformal FDTD on a BlueGene Supercomputer

This paper presents modeling and simulation utilizing a parallel conformal finite-difference time-domain (Yu and Mittra, 2003) code developed at the Electromagnetic Communication Laboratory, Pennsylvania State University, on a massively parallel supercomputer. Parallelization, scalability, and application to the modeling of high-end server electrical interconnects are examined.

Design optimization methodology for simultaneous bidirectional interface

This paper describes an electrical design optimization methodology for a high-speed point-to-point source-synchronous simultaneous bidirectional interface. These physical links are typically used to interconnect multiple processor subsystems to build symmetric multi-processor (SMP) systems, as well as to connect input/output (I/O) subsystems across relatively long distances. Major design issues such as attenuation, crosstalk, delay skew, impedance control and inter-symbol interference (ISI) are discussed for long and parallel external interconnections.

Statistical modeling of a multi-drop source synchronous bus

Using the source synchronous switching technique, high data rates can be achieved on the system board. When designing a source synchronous board, the goal is to minimize the variations in the differential delay between the data and strobe lines. This delay is often affected by jitter caused by power supply noise, cross talk, reflections and other signal integrity violations. This paper investigates the inter-relationships between electrical parameters in a printed circuit board to the physical manufacturing parameters for a source synchronous bus. Using sensitivity functions and statistical distributions of the physical parameters, the variations of the electrical parameters are computed. The correlation matrix between the electrical parameters can be used to understand the sensitivity of various electrical and physical parameters for the performance of the bus. This information can be used for redesigning boards by accounting for manufacturing variations.

Macro-modeling of non-linear pre-emphasis differential driver circuits

Differential signaling has become important in high speed digital and mixed signal systems because of its numerous advantages over single-ended signaling. Differential signaling reduces effects like simultaneous switching noise (SSN), electro magnetic interference (EMI) and crosstalk coupling. Signal integrity (SI) and timing analysis using differential drivers is computationally exhaustive due to increased complexity in design that includes features such as pre-compensation and slew rate control. Therefore, accurate macro-modeling of differential driver circuits for a quality design is a huge challenge. In this paper, a modeling technique based on recurrent neural network (RNN) is proposed to model differential driver circuits with and without pre-emphasis. Good accuracy is obtained in the test cases shown for the proposed modeling methodology at minimum computational cost.

Data center server packaging technology

The purpose of this paper is to describe BladeCenter/spl trade/ packaging technology and compare with 1U and 2U rack systems to illustrate the improvements. The power and thermal design challenges are described. The paper covers in detail power and thermal design advantages, and overall cost performance compared to 1U servers. A blade server is a rack-optimized server architecture designed to include the benefits of standardized 1U rack systems while eliminating the complications associated with these systems. The term BladeCenter refers to a chassis that can hold a number of hot-swappable devices called blades server. A blade sever is an independent server containing one or more processors, memory, disk storage, and network controllers. The BladeCenter was created to simplify the deployment of servers in an enterprise infrastructure.

Scalable driver I/O macromodels for statistical analysis

In this paper, scalable driver I/O macromodels have been proposed for efficient signal integrity and timing analysis of todays high-speed systems. Variations in semiconductor process, temperature, and power supply voltage affect the output voltage and current in driver circuits. The effect of these variations on driver and receiver circuits has been captured using Lagranges interpolation technique. In this paper, scalable macromodeling approach has been applied to differential driver circuits and single-ended driver and receiver circuits. Scalable driver and receiver circuits consume less CPU memory and simulation time compared to transistor-level driver and receiver circuits. The accuracy of scalable macromodels has been tested on various test cases for differential driver and single-ended driver-receiver circuits and results yielded good accuracy.

The Nittany Genome Project: a genetic algorithm approach to optimize a worst case bitstream for package simulation

This paper describes the use of a genetic algorithm to optimize short bitstream inputs to produce approximately worst case jitter in package simulation. Theory behind the algorithm and its applicability to a server memory subsystem simulation is summarized. Custom software utilizing this algorithm and an example of its use are presented.