Eric Luckowski

Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]

We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.

Materials Challenges for CMOS Junctions

Against a backdrop of the latest ITRS predictions for CMOS junctions, we compare methods for dopant introduction and activation, methods for making contact to these regions, and methods for measurement of material and device properties. As activation without diffusion (sub-melt laser, capacitor discharge flash, or solid phase epitaxy) becomes more feasible, the burden on Xj, Rsh and abruptness falls on the implanters, and the process margin appears slim, opening the door for other methods of doping. For contact resistance, a major component of transistor parasitics, we find that either a move to a different substrate, or from a single midgap silicide to two band-edge metals/silicides can be quite beneficial. Through the use of simple test structures, we describe a means of extracting each component of the parasitic resistance, facilitating development of materials for CMOS junctions.

Integration of UTR processes into MPU IC manufacturing flows

Low-k1 imaging, high-NA optics, pattern collapse, and the absorption of resist materials in 157-nm and EUV lithographies are driving down the thickness of the photoresist layer in integrated circuit fabrication processes. Although devices and test structures have been successfully fabricated with resist films thinner than 160 nm on various levels, the fabrication of working devices with high yield using ultrathin resist (UTR) integrations on multiple device layers has yet to be demonstrated. In the present work, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process. Similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography. The UTR NMOS transistors in this work have 10 pA/micrometers leakage and 400 (mu) A/micrometers drive currents, but the PMOS transistors do not perform as well. The line-edge roughness (LER) is 5-8 nm 3(sigma) depending upon exposure mask (binary vs. PSM) and substrate. Etching into 100 nm of crystalline Si reduces the LER to 4-7 nm 3(sigma) . The power spectral densities of the roughness have a Lorentzian shape, and most of the roughness occurs over length scales larger than 100 nm. Contact chains with electrical characteristics comparable to standard processes were fabricated with 120-nm thick resist films. Polysilicon as thick as 150 nm was etched successfully with 80-nm thick resist films and hardmasks.

Investigations of Metal Gate Electrodes on HfO 2 Gate Dielectrics

As traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO 2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate – HfO 2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal – dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO 2 electrodes is studied with Pt and LaB 6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO 2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO 2 -silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.

Single-layer and bilayer resist processes for EUV-type integrations

The high absorption of extreme ultraviolet (EUV) radiation by all materials necessitates the use of thin photoresist films with thicknesses less than 200 nm for EUV lithography to ensure good imaging. Thinning the resist thickness below 150 nm or even 100 nm may produce benefits such as increased sensitivity, larger process latitude, and increased resolution. However, these potential benefits as well as the required need for thin resists come at the expense of reduced etch resistance. EUV lithography will require the use of some type of thin imaging technique such as top-surface imaging, bilayer resists, or single layer resists with hardmasks in order to achieve the necessary etch resistance. In this paper, we discuss results that demonstrate the feasibility of using thin resist approaches for fabricating working devices. We have successfully fabricated working 130-nm-node SRAMs using a single layer 248 nm ultrathin resist (< 150-nm-thick) with a hardmask for both gate and contact layers on the same wafer. This result represents the first demonstration of working devices fabricated using ultrathin resists on multiple device layers. We also present initial patterning experiments using a 193 nm bilayer resist for brightfield applications such as the gate layer, and compare imaging performance to that of a 193 nm single layer resist. The advantages and disadvantages of the single layer and bilayer approaches are discussed.

Fabrication of integrated circuits with high yield using ultra-thin resist processes

We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.