Mark V. Raymond

Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies

High precision metal-insulator-metal capacitors with a capacitance density of 1.6 fF/um/sup 2/ and metal thin film resistors of 50 ohm/sq. sheet resistance and a negative temperature coefficient of resistivity smaller than 100 ppm//spl deg/C have been integrated in a dual-inlaid Cu-based backend for mixed-signal applications. These devices deliver reduced parasitics, better linearity, lower temperature coefficients, lower noise, and better matching as compared to current silicon based devices.

Improved Electrical Properties of ALD

The impact of ultrathin metal underlayer on physical and electrical properties of Hf<i> _x </i>Zr_1- <i> _x </i>O₂(x=~0.4) after high-temperature processing was investigated. An ~5-Aring Zr, ~5-Aring Hf, ~10-Aring Hf metal layer was sputter deposited prior to Hf<i> _x </i>Zr_1- <i> _x </i>O₂ growth. Cross-sectional transmission electron microscopy and secondary ions mass spectrometry analysis confirmed no Zr or Hf silicide formation between the high-<i>k</i> film and Si substrate even after 1000degC processing. No significant increase in equivalent oxide thickness or gate leakage current is observed on devices with metal underlayer. Furthermore, devices with a 5-Aring-thick Zr underlayer exhibited lower threshold voltage, higher mobility, and improved charge trapping characteristics.

\hbox{Hf}_{x} \hbox{Zr}_{1 - x}\hbox{O}_{2}

We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.

Dielectrics Deposited on Ultrathin PVD Zr Underlayer

Metal thin film resistors have been integrated into a damascene-copper multilayer metallization system for mixed-signal BiCMOS technology platforms. The thin film process can be adjusted to achieve resistors with very low temperature coefficients, high linearity, low noise, and improved matching as compared to resistors based on implanted silicon or polysilicon processing. In addition, improvement in terms of good RF performance was observed.

Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]

As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 A equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO 2 as candidate metals for dual-metal gate CMOS using HfO 2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO 2 n-MOSFETs.

Tantalum nitride thin film resistors for integration into copper metallization based RF-CMOS and BiCMOS technology platforms

Long recognized as the best potential solution to the continued scaling of the onetransistor/one-capacitor standalone dynamic random access memory (DRAM) beyond a gigabit, barium strontium titanate (BST) and other high permittivity dielectrics are fast becoming enablers to embedding large amounts of memory into a high performance logic process. System requirements such as granularity, bandwidth, fill frequency, and power pose major challenges to the use of high density standalone DRAM, leading to the current push for embedded solutions where very wide buses are possible. As a result, projected embedded memory sizes are rapidly approaching that of the standalone products, and with the high wafer cost of the combined logic plus memory process, bit cell scaling is critical. The BST memory cell, with its low thermal budget processing, very high charge storage density, and high conductivity metal electrodes has the potential to be efficiently embedded with traditional logic flows if the materials and integration challenges of the required three dimensional (3D) bit cell capacitors can be solved. BST materials properties such as dielectric relaxation, interface capacitance, and resistance degradation and their impact on capacitor scaling will be reviewed along with the electrode materials issues associated with certain 3D capacitor designs. The scaling limits of BST bit cells in the deep sub-micron regime will be discussed.

Evaluation of Candidate Metals for Dual-Metal Gate CMOS with HfO 2 Gate Dielectric

Dielectric capping layer and electrode alloying approaches for tuning the effective work function and effective oxide thickness of metal oxide semiconductor transistors are compared. TaMgC and MoAlN electrodes are compared to MgO and Al2O3 capping layers for n-type and p-type transistors respectively. Results indicate that by incorporating the Mg or Al into the gate electrode instead of into the dielectric capping layer reductions in threshold voltage can be achieved, but with the added benefit of an effective oxide thickness reduction. SIMS results suggest that the threshold voltage shift is likely caused by the inward diffusion of Mg or Al though the gate dielectric towards the bottom interface layer. The limitations of each approach for work function engineering are discussed.

Barium Strontium Titanate Capacitors for Embedded Dram

Measurements of the equilibrium oxygen activity as a function of temperature at constant defect concentrations have been used to obtain the chemical enthalpy of oxidation, i.e. the reaction to add a stoichiometric excess of oxygen and trapped holes, for acceptor-doped BaTiO3, SrTiO3, and CaTiO3. The values are −0.15, +0.21, and −0.28 eV, respectively. Combined with the enthalpy of oxidation obtained from equilibrium conductivity measurements, i.e. the reaction to form free holes, the depths of the acceptor hole traps are found to be 0.54, 0.60, and 1.22 eV, respectively.