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Dive into the research topics where Olubunmi Adetutu is active.

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Featured researches published by Olubunmi Adetutu.


international electron devices meeting | 2003

Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]

Srikanth B. Samavedam; L.B. La; Philip J. Tobin; Bruce E. White; C. Hobbs; Leonardo Fonseca; Alexander A. Demkov; Jamie Schaeffer; Eric Luckowski; A. Martinez; Mark V. Raymond; D. Triyoso; D. Roan; V. Dhandapani; R. Garcia; S.G.H. Anderson; K. Moore; Hsing-Huang Tseng; C. Capasso; Olubunmi Adetutu; David C. Gilmer; William J. Taylor; Rama I. Hegde; John M. Grant

We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.


MRS Proceedings | 2004

Investigations of Metal Gate Electrodes on HfO 2 Gate Dielectrics

Jamie Schaeffer; Sri Samavedam; Leonardo Fonseca; C. Capasso; Olubunmi Adetutu; David C. Gilmer; C. Hobbs; Eric Luckowski; R. B. Gregory; Zhi-Xiong Jiang; Yong Liang; K. Moore; Darrell Roan; Bich-Yen Nguyen; Phil Tobin; Bruce E. White

As traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO 2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate – HfO 2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal – dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO 2 electrodes is studied with Pt and LaB 6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO 2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO 2 -silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.


Archive | 2001

Semiconductor device and method of formation

Alexander L. Barr; Suresh Venkatesan; David Clegg; Rebecca G. Cole; Olubunmi Adetutu; Stuart E. Greer; Brian G. Anthony; Ramnath Venkatraman; Gregor Braeckelmann; Douglas M. Reber; Stephen R. Crown


Archive | 2000

Process for forming a high-K gate dielectric

Vidya Kaushik; Bich-Yen Nguyen; Olubunmi Adetutu; C. Hobbs


Archive | 2001

Transistor metal gate structure that minimizes non-planarity effects and method of formation

John M. Grant; Olubunmi Adetutu; Yolanda Musgrove


Archive | 1997

Semiconductor device having a metal containing layer overlying a gate dielectric

Bich-Yen Nguyen; J. Olufemi Olowolafe; Bikas Maiti; Olubunmi Adetutu; Philip J. Tobin


Archive | 1999

Semiconductor device conductive bump and interconnect barrier

Alexander L. Barr; Suresh Venkatesan; David Clegg; Rebecca G. Cole; Olubunmi Adetutu; Stuart E. Greer; Brian G. Anthony; Ramnath Venkatraman; Gregor Braeckelmann; Douglas M. Reber; Stephen R. Crown


Archive | 2001

Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same

Olubunmi Adetutu; Yeong-Jyh T. Lii; Paul A. Grudowski


Archive | 2002

Method of forming semiconductor device including interconnect barrier layers

Alexander L. Barr; Suresh Venkatesan; David Clegg; Rebecca G. Cole; Olubunmi Adetutu; Stuart E. Greer; Brian G. Anthony; Ramnath Venkatraman; Gregor Braeckelmann; Douglas M. Reber; Stephen R. Crown


Archive | 1998

Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation

Kevin D. Lucas; Olubunmi Adetutu; C. Hobbs; Yolanda Musgrove; Yeong-Jyh Tom Lii

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