Eric R. Miller

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

SiGe FinFET for practical logic libraries by mitigating local layout effect

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Advanced in-line metrology strategy for self-aligned quadruple patterning

Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed design into a quarter of its original pitch. Due to the number of multiple process steps required for the pitch splitting in SAQP, the process error propagates through each deposition and etch, and accumulates at the final step into structure variations, such as pitch walk and poor critical dimension uniformity (CDU). They can further affect the downstream processes and lower the yield. The impact of this error propagation becomes significant for advanced technology nodes when the process specifications of device design CD requirements are at nanometer scale. Therefore, semiconductor manufacturing demands strict in-line process control to ensure a high process yield and improved performance, which must rely on precise measurements to enable corrective actions and quick decision making for process development. This work aims to provide a comprehensive metrology solution for SAQP. During SAQP process development, the challenges in conventional in-line metrology techniques start to surface. For instance, critical-dimension scanning electron microscopy (CDSEM) is commonly the first choice for CD and pitch variation control. However, it is found that the high aspect ratio at mandrel level processes and the trench variations after etch prevent the tool from extracting the true bottom edges of the structure in order to report the position shift. On the other hand, while the complex shape and variations can be captured with scatterometry, or optical CD (OCD), the asymmetric features, such as pitch walk, show low sensitivity with strong correlations in scatterometry. X-ray diffraction (XRD) is known to provide useful direct measurements of the pitch walk in crystalline arrays, yet the data analysis is influenced by the incoming geometry and must be used carefully. A successful implementation of SAQP process control for yield improvement requires the metrology issues to be addressed. By optimizing the measurement parameters and beam configurations, CDSEM measurements distinguish each of the spaces corresponding to the upstream mandrel processes and report their CDs separately to feed back to the process team for the next development cycle. We also utilize the unique capability in scatterometry to measure the structure details in-line and implement a “predictive” process control, which shows a good correlation between the “predictive” measurement and the cross-sections from our design of experiments (DOE). The ability to measure the pitch walk in scatterometry was also demonstrated. This work also explored the frontier of in-line XRD capability by enabling an automatic RSM fitting on tool to output pitch walk values. With these advances in metrology development, we are able to demonstrate the impacts of in-line monitoring in the SAQP process, to shorten the patterning development learning cycle to improve the yield.

Nitride etching with hydrofluorocarbons III: Comparison of C4H9F and CH3F for low-k′ nitride spacer etch processes

The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These unique characteristics of C4H9F can facilitate innovative plasma etch processes for nitride-based materials patterning in a wide range of applications.The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These uniq...