Stuart A. Sieg

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

DSA patterning options for FinFET formation at 7nm node

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.

DSA patterning options for logics and memory applications

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Advanced in-line metrology strategy for self-aligned quadruple patterning

Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed design into a quarter of its original pitch. Due to the number of multiple process steps required for the pitch splitting in SAQP, the process error propagates through each deposition and etch, and accumulates at the final step into structure variations, such as pitch walk and poor critical dimension uniformity (CDU). They can further affect the downstream processes and lower the yield. The impact of this error propagation becomes significant for advanced technology nodes when the process specifications of device design CD requirements are at nanometer scale. Therefore, semiconductor manufacturing demands strict in-line process control to ensure a high process yield and improved performance, which must rely on precise measurements to enable corrective actions and quick decision making for process development. This work aims to provide a comprehensive metrology solution for SAQP. During SAQP process development, the challenges in conventional in-line metrology techniques start to surface. For instance, critical-dimension scanning electron microscopy (CDSEM) is commonly the first choice for CD and pitch variation control. However, it is found that the high aspect ratio at mandrel level processes and the trench variations after etch prevent the tool from extracting the true bottom edges of the structure in order to report the position shift. On the other hand, while the complex shape and variations can be captured with scatterometry, or optical CD (OCD), the asymmetric features, such as pitch walk, show low sensitivity with strong correlations in scatterometry. X-ray diffraction (XRD) is known to provide useful direct measurements of the pitch walk in crystalline arrays, yet the data analysis is influenced by the incoming geometry and must be used carefully. A successful implementation of SAQP process control for yield improvement requires the metrology issues to be addressed. By optimizing the measurement parameters and beam configurations, CDSEM measurements distinguish each of the spaces corresponding to the upstream mandrel processes and report their CDs separately to feed back to the process team for the next development cycle. We also utilize the unique capability in scatterometry to measure the structure details in-line and implement a “predictive” process control, which shows a good correlation between the “predictive” measurement and the cross-sections from our design of experiments (DOE). The ability to measure the pitch walk in scatterometry was also demonstrated. This work also explored the frontier of in-line XRD capability by enabling an automatic RSM fitting on tool to output pitch walk values. With these advances in metrology development, we are able to demonstrate the impacts of in-line monitoring in the SAQP process, to shorten the patterning development learning cycle to improve the yield.

Comprehensive analysis of line-edge and line-width roughness for EUV lithography

Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.

An OCD perspective of line edge and line width roughness metrology

Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.

Directed self-assembly patterning for forming fin field effect transistors

Directed self-assembly (DSA) of block copolymers (BCPs) is a method used to extend the scope of optical lithography, which uses a topographical or chemical guiding pattern to direct BCPs to form the desired morphology at a predetermined location. The properties of the BCPs control the feature size and uniformity of the resulting structures. This technique has become the focus of attention for use in semiconductors, hard disk drives, and non-volatile memory owing to its potential for multiplication of pattern density and defect rectification. Studies have been carried out on the compatibility of DSA with 193nm immersion lithography (193i) and high-volume manufacturing (HVM), as well as its defectivity and demonstration in devices. These studies confirm that DSA is a suitable candidate for widening the scope of lithography rather than merely being a lab-scale nanofabrication method.1–5 One potential application of DSA in semiconductor manufacturing is for creating a dense array of fins for fin field effect transistors. Conventional methods for the formation of fins rely on sidewall image transfer, self-aligned double patterning, or self-aligned quadruple patterning (SAQP) to create a ‘sea of fins,’ followed by two or more lithographic customization steps that remove or preserve part of the array. Customization patterns that are parallel to fins are critical, because the edges of the shapes need to be accurately placed between two adjacent fins. The tolerance for placement error, including overlay, Figure 1. Fins are formed via either directed self-assembly using chemoepitaxy (chemo DSA) or hybrid DSA. The stacks comprise, from top to bottom: in chemo DSA, an upper silicon nitride (SiN) layer, amorphous carbon (aC), silicon oxide (Ox), a lower SiN layer, and silicon; in hybrid DSA, a neutral layer, Ox, an organic planarization layer (OPL), Ox, SiN, and silicon. BCP: Block copolymer. HMO: Hard mask open. NTD: Negative tone development. PMMA: Polymethyl methacrylate. xPS: Crosslinkable polystyrene.

Successes and frontiers in extreme UV patterning

As a semiconductor patterning technique, extreme UV (EUV) lithography has stood at the cusp of viability for over a decade. In this technique, simple single-level patterning is conducted at an exposure wavelength of 13.5nm. EUV lithography brings the promise of delivering the node-by-node feature scaling that is required by the semiconductor industry, but the delay in its implementation has necessitated the adoption of 193nm immersion (193i) multi-patterning techniques to deliver the same scaling, albeit at obvious extra cost and complexity. While the industry has been stuck at 193i-based patterning, the initial lithography and etch steps have remained at relatively unchanged dimensions and have used well-known (and optimized) materials. The step down to EUV-based lithography (i.e., from about 80nm pitch for 193i to about 30nm pitch) therefore brings the need for much thinner, and potentially more etch-selective, patterning materials in the trilayer lithography stack so that the dimensions and aspect ratios required for etch transfer can be achieved. In other words, to meet high-volume manufacturing (HVM) needs, a decade’s worth of industry yield learning must be revised in less than five years (see Figure 1). Over the last couple of years, the industry has made significant progress in tackling many of the main impediments to the adoption of EUV in HVM. Most notably, there have been significant improvements to exposure tool throughput, reliability, and variance control,1 as well as patterning materials with which it is possible to achieve the small dimensions required.2 In addition, we have demonstrated key aspects of EUV mask infrastructure that provide further confidence in the technology as an HVM solution.3, 4 Nevertheless, the implementation of EUV as part of the integrated patterning process is still a remaining challenge. Figure 1. Moving from 193nm immersion (193i) to extreme UV (EUV) lithography (litho) involves a large step down in aspect ratios and pitch size. The change in patterning technique also brings a number of ‘unknowns’ that are related to the materials and processes involved. Cartoons are shown to scale.

Assessments of image-based and scatterometry-based overlay targets

Having a well designed overlay metrology target is one of the ways to improve on-product overlay performance. The traditional screening method in which multiple targets types are added to successive reticle tape outs and then evaluated by trial-and-error may not suffice for the 7nm node and beyond. For instance, although segmentation of image-based overlay target has been reported by many as a means for improving overlay measurement, we find that segmentation does not guarantee improvement. In fact it can be undesirable. Fundamental understandings of metrology and wafer process are required to properly design the targets and carefully optimize them for a given process stack involving multilevel measurement. This paper investigates the Blossom, AIM, and scatterometry targets at the FEOL, MOL, and BEOL patterning levels in 7nm node to gain knowledge needed in order to comprehensively map out the overlay target solutions for future nodes.