Fee Li Lie

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

DSA patterning options for FinFET formation at 7nm node

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.

SiGe FinFET for practical logic libraries by mitigating local layout effect

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Fin formation using graphoepitaxy DSA for FinFET device fabrication

A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.

Directed self-assembly patterning for forming fin field effect transistors

Directed self-assembly (DSA) of block copolymers (BCPs) is a method used to extend the scope of optical lithography, which uses a topographical or chemical guiding pattern to direct BCPs to form the desired morphology at a predetermined location. The properties of the BCPs control the feature size and uniformity of the resulting structures. This technique has become the focus of attention for use in semiconductors, hard disk drives, and non-volatile memory owing to its potential for multiplication of pattern density and defect rectification. Studies have been carried out on the compatibility of DSA with 193nm immersion lithography (193i) and high-volume manufacturing (HVM), as well as its defectivity and demonstration in devices. These studies confirm that DSA is a suitable candidate for widening the scope of lithography rather than merely being a lab-scale nanofabrication method.1–5 One potential application of DSA in semiconductor manufacturing is for creating a dense array of fins for fin field effect transistors. Conventional methods for the formation of fins rely on sidewall image transfer, self-aligned double patterning, or self-aligned quadruple patterning (SAQP) to create a ‘sea of fins,’ followed by two or more lithographic customization steps that remove or preserve part of the array. Customization patterns that are parallel to fins are critical, because the edges of the shapes need to be accurately placed between two adjacent fins. The tolerance for placement error, including overlay, Figure 1. Fins are formed via either directed self-assembly using chemoepitaxy (chemo DSA) or hybrid DSA. The stacks comprise, from top to bottom: in chemo DSA, an upper silicon nitride (SiN) layer, amorphous carbon (aC), silicon oxide (Ox), a lower SiN layer, and silicon; in hybrid DSA, a neutral layer, Ox, an organic planarization layer (OPL), Ox, SiN, and silicon. BCP: Block copolymer. HMO: Hard mask open. NTD: Negative tone development. PMMA: Polymethyl methacrylate. xPS: Crosslinkable polystyrene.